M41T256YMT7 STMicroelectronics, M41T256YMT7 Datasheet
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M41T256YMT7
Specifications of M41T256YMT7
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M41T256YMT7 Summary of contents
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Features ■ 5V operating voltage ■ Serial interface supports extended I addressing (400kHz) ■ Automatic switchover and deselect circuitry ■ Power-fail deselect voltages: – M41T256Y 4 5.5V 4.2V < V < 4.5V PFD ...
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Contents 1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary The M41T256Y Serial TIMEKEEPER organized as 32K words by 8 bits. A built-in 32.768kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see and are configured in binary coded decimal (BCD) format. Addresses and data are ...
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Figure 1. Logic diagram SCL SDA TP 1. For 44-pin SNAPHAT (MT) package only. Table 1. Signal names FT RST SCL SDA RST M41T256Y AI04754b Frequency test (open drain) Reset ...
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Figure 2. 44-pin SOIC (MH - snaphat) Figure 3. Block diagram SDA SCL Crystal TP V BAT 1. Open drain output 8/ RST 5 ...
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Operating modes The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 256K bytes contained in the device can then be ...
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Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. 2.1.3 Stop data transfer A change in the state of the data line, from ...
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Figure 4. Serial bus data transfer sequence (SCL) CLOCK (SDA) DATA START CONDITION Figure 5. Acknowledgement sequence START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED 1 2 ...
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Figure 6. Bus timing requirements sequence SDA tBUF SCL P S Table 2. AC characteristics Symbol f SCL clock frequency SCL Time the bus must be free before a new transmission can t BUF start t SDA and SCL fall ...
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An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Note: Address pointer ...
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Figure 8. Read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 9. Alternate read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X 14/30 BYTE BYTE S ADDRESS ...
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Write mode In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol is shown in Figure 10 on page '0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses ...
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Sleep mode In order to minimize the battery current draw while in storage, the M41T256Y provides the user with a battery “sleep mode,” which disconnects the RAM memory array from the external Lithium battery normally used to provide non-volatile ...
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Clock operation Year, month, and date are contained in the last three registers of the TIMEKEEPER register map (see Table 3 on page day (day of week). Finally, there are the registers containing the seconds, minutes, and hours, respectively. ...
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Table 3. TIMEKEEPER Address D7 7FFFh 7FFEh 0 7FFDh 0 7FFCh BL 7FFBh 0 7FFAh 0 7FF9h ST 7FF8h WC 7FF7h 7FF6h X 7FF5h X 7FF4h X 7FF3h X 7FF2h X 7FF1h X 7FF0h X Keys Sign bit ...
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Tamper indication circuit The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable bit (TEB) ...
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If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified binary 6 is loaded, the ...
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The first involves setting the clock, letting it run for a month and comparing known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under ...
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Table 8. DC characteristics Sym Parameter Battery current OSC ON I BAT Battery current OSC OFF I Supply current CC1 I Supply current (standby) CC2 I Input leakage current LI (2) I Output leakage current LO V Input high voltage ...
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Figure 14. Power down/up mode AC waveforms PFD (max) V PFD (min INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) Table 10. Power down/up AC characteristics Symbol ( (max ...
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Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal outline Note: Drawing is not to scale. Table 12. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data Symb Typ ...
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Part numbering Table 13. Ordering information scheme Example: Device type M41T Supply voltage and write protect voltage 256Y = V = 4.5 to 5.5V 4.2 to 4.5V CC PFD Package ( SOH44 Temperature range 7 ...
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Revision history Table 15. Document revision history Date Version February 2002 26-Apr-02 31-May-02 03-Jul-02 12-Jul-02 29-Jul-02 20-Dec-02 04-Jan-03 26-Mar-03 15-Jun-04 16-Apr-2007 09-Nov-2007 1.0 First Issue 1.1 Addition of “Tamper Event Time-Stamp” text Add Sleep Mode, 44-pin with SNAPHAT package ...
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