ISPGDX80VA-3TN100 Lattice, ISPGDX80VA-3TN100 Datasheet - Page 5

• Manufacturer Part Number: ISPGDX80VA-3TN100
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX80VA-3TN100

• Maximum Dual Supply Voltage: 1.95 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Single
• Configuration: 40 x 40
• Package / Case: PLCC-28
• Input Level: TTL
• Output Level: LVTTL, TTL
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Group A
D11 MUX Out
I/O Group B
D12 MUX Out
I/O Group C
D14 MUX Out
I/O Group D
D15 MUX Out
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX80VA, I/O D13
It can be seen from Figure 3 that if the D11 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
The ispGDXVA can implement MUXes up to 16 bits wide
in a single level of logic, but care must be taken when
combining adjacent I/O cell outputs with direct MUX
inputs. Any particular combination of adjacent I/O cells as
MUX inputs will dictate what I/O groups (A, B, C or D) can
be routed to the remaining inputs. By properly choosing
the adjacent I/O cells, all of the MUX inputs can be
utilized.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX80VA)
Reflected
I/O Cells
I/O Cells
Normal
B10
B11
B12
B13
D10
D11
D12
D13
D6
D7
D8
D9
B6
B7
B8
B9
ispGDX80VA I/O Cell
MUXOUT
Data A/
B12
B13
B14
B15
D10
D11
D10
D11
D8
D9
D8
D9
B4
B5
B6
B7
Crossbar
Switch
4 x 4
MUXOUT
Data B/
B11
B12
B13
B14
D10
D10
D11
D12
D7
D8
D9
D9
B5
B6
B7
B8
MUXOUT
Data C/
B10
B11
B12
D11
D12
D13
D14
B10
D5
D6
D7
D8
B9
B7
B8
B9
S1
.m0
.m1
.m2
.m3
MUXOUT
S0
Data D/
B10
B11
D12
D13
D14
D15
B10
B11
B8
B9
D4
D5
D6
D7
B8
B9
D13
5
Slew Rate Control
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate op-
tions.
Open Drain Control
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
User-Programmable I/Os
The ispGDX80VA features user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX80VA uses a VCCIO pin to provide
the 2.5V reference voltage when used.
PCI Compatible Drive Capability
The ispGDX80VA supports PCI compatible drive capa-
bility for all I/Os.
Special Features
Specifications ispGDX80VA