DS26504LN Maxim Integrated Products, DS26504LN Datasheet - Page 3

• Manufacturer Part Number: DS26504LN
• Description: Network Controller & Processor ICs T1-E1-J1-64kHz Compo 4kHz Composite Clock
• Manufacturer: Maxim Integrated Products

Specifications of DS26504LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64

8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
8.1
9.1
9.2
11.1
11.2
11.3
12.1
12.2
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
15.1
15.2
16.1
16.2
17.1
17.2
17.3
17.4
12.1.1
13.2.1
13.2.2
13.2.3
13.3.1
13.3.2
13.3.3
13.3.4
G.703 Level A ................................................................................................................................................... 101
T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40
E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46
I/O PIN CONFIGURATION OPTIONS ............................................................................53
T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................56
E1 SYNCHRONIZATION STATUS MESSAGE ..............................................................65
LINE INTERFACE UNIT (LIU) ........................................................................................80
LOOPBACK CONFIGURATION.....................................................................................99
64KHZ SYNCHRONIZATION INTERFACE..................................................................100
6312KHZ SYNCHRONIZATION INTERFACE..............................................................102
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................103
T1 C
E1 C
E1 I
T1 B
T
R
S
A
LIU O
LIU R
LIU T
MCLK P
J
CMI (C
LIU C
R
C
R
T
R
T
I
T
B
B
NSTRUCTION
ITTER
RANSMIT
RANSMIT
RANSMIT
EST
A
LTERNATE
OUNDARY
YPASS
ECEIVE
ECOMMENDED
OMPONENT
ECEIVE
ECEIVE
Sa Bit Change of State......................................................................................................................... 66
Receive Level Indicator........................................................................................................................ 81
Receive G.703 Section 13 Synchronization Signal ............................................................................. 82
Monitor Mode ....................................................................................................................................... 82
Transmit Short-Circuit Detector/Limiter................................................................................................ 83
Transmit Open-Circuit Detector ........................................................................................................... 83
Transmit BPV Error Insertion ............................................................................................................... 83
Transmit G.703 Section 13 Synchronization Signal (E1 Mode)........................................................... 83
/S
NFORMATION
IT
ONTROL
I
ONTROL
R
RANSMITTER
ECEIVER
ONTROL
B
PERATION
-O
A
ODE
EGISTERS
IT
R
RE
TTENUATOR
RIENTED
BOC ............................................................................................................................57
64
6312
A
EGISTER
BOC ..........................................................................................................................56
64
6312
-S
CCESS
S
K
S
M
H
K
S
CAN
R
A
R
CALER
R
ARK
R
H
K
............................................................................................................................81
PECIFICATIONS
Z
/S
EGISTERS
EGISTERS
EGISTER
H
K
..........................................................................................................................81
EGISTERS
Z
C
S
I
H
......................................................................................................................108
Z
R
S
R
IRCUITS
YNCHRONIZATION
C
B
I
B
......................................................................................................................82
Z
NVERSION
S
...................................................................................................................108
EGISTERS
YNCHRONIZATION
EGISTER
IT
ODE
ASED ON
...................................................................................................................83
S
YNCHRONIZATION
..................................................................................................................83
A
YNCHRONIZATION
CCESS
...........................................................................................................107
(BOC) C
............................................................................................................40
...........................................................................................................46
...........................................................................................................93
..........................................................................................................85
.....................................................................................................108
......................................................................................................49
) O
CRC4 M
.....................................................................................................95
B
ASED ON
PTION
ONTROLLER
I
NTERFACE
I
NTERFACE
ULTIFRAME
I
.......................................................................................84
NTERFACE
I
3 of 129
NTERFACE
D
OUBLE
............................................................................56
O
O
PERATION
-F
......................................................................65
O
PERATION
O
PERATION
RAME
PERATION
..........................................................77
.....................................................100
...................................................101
.................................................102
...............................................102