DS26504LN Maxim Integrated Products, DS26504LN Datasheet - Page 64

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DS26504LN

Manufacturer Part Number
DS26504LN
Description
Network Controller & Processor ICs T1-E1-J1-64kHz Compo 4kHz Composite Clock
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS26504LN

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
150 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Note: Also used to insert Fs framing pattern in D4 framing mode.
The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte-basis into the outgoing T1 data
stream. The LSB is transmitted first.
Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code.
Bit 1: Transmit FDL Bit 1 (TFDL1)
Bit 2: Transmit FDL Bit 2 (TFDL2)
Bit 3: Transmit FDL Bit 3 (TFDL3)
Bit 4: Transmit FDL Bit 4 (TFDL4)
Bit 5: Transmit FDL Bit 5 (TFDL5)
Bit 6: Transmit FDL Bit 6 (TFDL6)
Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.
TFDL7
7
0
0
TFDL6
TFDL
Transmit FDL Register
51h
6
0
0
TFDL5
5
0
0
TFDL4
4
0
1
64 of 129
TFDL3
3
0
1
TFDL2
2
0
1
TFDL1
1
0
0
TFDL0
0
0
0

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