DS26504LN Maxim Integrated Products, DS26504LN Datasheet - Page 50

• Manufacturer Part Number: DS26504LN
• Description: Network Controller & Processor ICs T1-E1-J1-64kHz Compo 4kHz Composite Clock
• Manufacturer: Maxim Integrated Products

Specifications of DS26504LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64

Table 9-2. E1 Alarm Criterion
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bits 0 to 3: Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip.
ID0 is the LSB of a decimal code that represents the chip revision.
Bits 4 to 7: Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26504 ID. The DS26504 ID is
0010.
V52LNK
ALARM
RDMA
RLOF
RLOS
RUA1
RRA
DS26502 = 0000
DS26503 = 0001
DS26504 = 0010
ID7
An RLOF condition exists on power-up
prior to initial synchronization, when a
resync criterion has been met, or when a
manual resync has been initiated via
E1RCR.0
255 or 2048 consecutive zeros received as
determined by E1RCR.0
Bit 3 of non-align frame set to one for
three consecutive occasions
Fewer than three zeros in two frames (512
bits)
Bit 6 of time slot 16 in frame 0 has been
set for two consecutive multiframes
Two out of three Sa7 bits are zero
X
7
0
ID6
IDR
Device Identification Register
10h
SET CRITERION
X
6
0
ID5
X
5
0
ID4
X
4
0
50 of 129
ID3
—
In 255-bit times, at least 32
ones are received
Bit 3 of non-align frame set to
zero for three consecutive
occasions
More than two zeros in two
frames (512 bits)
—
N
X
—
3
CLEAR CRITERION
ID2
N
X
2
DS26504 T1/E1/J1/64KCC BITS Element
ID1
N
X
1
ID0
N
X
0
G.775/G.962
SPEC.
1.6.1.2
O.162
O.162
G.965
2.1.4
ITU
—