78Q8430-128CGTR/F Maxim Integrated Products, 78Q8430-128CGTR/F Datasheet - Page 33

• Manufacturer Part Number: 78Q8430-128CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
The CAM is a 128-word by 15-bit wide content addressable memory. When a reference data word is
applied to the CAM, the result is the highest numbered address that contains a data word that matches
the reference. Each data word contained in the CAM also contains 15 mask bits that conditionally disable
individual data bits from preventing a match. Address 0 is reserved and can never match such that no
reference data can ever result in a CAM address of zero. Address 1 is also reserved and always
matches such that a reference word that does not match any entry in the CAM will give a result of one.
Associated with each CAM entry is a control word. When a reference data word is presented to the CAM
and an address results, the control word associated with that address is passed to the control logic that
determines the next action taken by the packet classifier.
The control logic can execute any of the following actions:
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To facilitate classification, the control logic contains a general purpose 8-bit register, ‘X’ and a 5-bit
counter, ‘C’. The ‘X’ register can be used to store a packet byte or a CAM result for later use. The
counter can be used as a loop index to iterate a set of rules a fixed number of times. The TOC action is
used to set the counter and the DEC action is used to decrement the counter. When a DEC action
causes the counter to expire, the loop is broken by decrementing the actual CAM address of the rule that
executed the DEC action for the purposes of the next CAM reference word. To prevent ambiguity, the
rule immediately below a rule that uses the DEC action should generally not be used.
Additionally, the control logic is responsible for generating the next 15-bit CAM match word by
concatenating the next 8-bit packet data byte or the ‘X’ register value with the 7-bit address of the current
CAM match. At the beginning of the packet, the previous CAM match is initialized to zero as is the
control logic ‘X’ register. The CAM address of zero is reserved and will never result from a CAM match
such that the first data byte in the frame is guaranteed to be the only byte that is accompanied by a zero
value for the previous hit. In other words, a CAM rule with a specified value for the previous hit of zero
will only match the first byte of the frame.
Rev. 1.2
Set the most significant byte of the pause counter.
Set the least significant byte of the pause counter.
Start the pause timer.
Cause the packet to be dropped.
Wake the host from power down mode (starts the HNR timer).
Interrupt the host.
Manipulate the classification result reported in the RPSR.
Identify multicast/broadcast frames for RMON statistics.
Identify the Len/Type field for frame size checking.
Identify the IP header for checksum checking.
Data Byte
EOF
Figure 14: Classification Architecture
WCS
CAM Address
Control Signals
Reference
Word
CAM
78Q8430 Data Sheet
33