LX128EV-32F208C Lattice, LX128EV-32F208C Datasheet - Page 39

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LX128EV-32F208C

Manufacturer Part Number
LX128EV-32F208C
Description
Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 3.3V, 3.2ns
Manufacturer
Lattice
Datasheet

Specifications of LX128EV-32F208C

Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
3.3 V
Supply Type
Triple
Configuration
128 x 128
Package / Case
FPBGA-208
Data Rate
21 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LX128EV-32F208C
Manufacturer:
SHPA
Quantity:
1
Part Number:
LX128EV-32F208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters
Lattice Semiconductor
Optional Adders
t
t
t
Slow Slew
LVTTL_out
LVCMOS_18_4mA_out
LVCMOS_18_5.33mA_out
LVCMOS_18_8mA_out
LVCMOS_18_12mA_out
LVCMOS_25_4mA_out
LVCMOS_25_5.33mA_out
LVCMOS_25_8mA_out
LVCMOS_25_12mA_out
LVCMOS_25_16mA_out
LVCMOS_33_4mA_out
LVCMOS_33_5.33mA_out
LVCMOS_33_8mA_out
LVCMOS_33_12mA_out
LVCMOS_33_16mA_out
LVCMOS_33_20mA_out
AGP_1X_out
BLVDS_out
CTT25_out
CTT33_out
GTL+_out
HSTL_I_out
HSTL_III_out
HSTL_IV_out
INDIO
PLL_SEC_DELAY
IOO
Output Adjusters
Parameter
Input Delay
Secondary PLL Output
Delay
Using Slow Slew (LVTTL and
LVCMOS Outputs Only)
Using 3.3V TTL Drive
Using 1.8V CMOS Standard,
4mA Drive
Using 1.8V CMOS Standard,
5.33mA Drive
Using 1.8V CMOS Standard,
8mA Drive
Using 1.8V CMOS Standard,
12mA Drive
Using 2.5V CMOS Standard,
4mA Drive
Using 2.5V CMOS Standard,
5.33mA Drive
Using 2.5V CMOS Standard,
8mA Drive
Using 2.5V CMOS Standard,
12mA Drive
Using 2.5V CMOS Standard,
16mA Drive
Using 3.3V CMOS Standard,
4mA Drive
Using 3.3V CMOS Standard,
5.33mA Drive
Using 3.3V CMOS Standard,
8mA Drive
Using 3.3V CMOS Standard,
12mA Drive
Using 3.3V CMOS Standard,
16mA Drive
Using 3.3V CMOS Standard,
20mA Drive
Using AGP 1x Standard
Using Bus Low Voltage Dif-
ferential Signaling (BLVDS)
Using CTT 2.5v
Using CTT 3.3v
Using GTL+
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
Using HSTL 2.5V, Class IV
Description
Min.
36
-3
Max.
1.50
1.30
0.90
1.20
0.30
0.30
0.00
0.00
1.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
0.30
0.60
1.00
0.30
0.20
0.50
0.50
0.60
0.60
Min.
-32
Max.
1.50
1.30
0.90
1.20
0.30
0.30
0.00
0.00
1.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
0.30
0.60
1.00
0.30
0.20
0.50
0.50
0.60
0.60
ispGDX2 Family Data Sheet
Min.
-35
Max.
1.50
1.30
0.90
1.20
0.30
0.30
0.00
0.00
1.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
0.30
0.60
1.00
0.30
0.20
0.50
0.50
0.60
0.60
Min.
-5
Max.
2.50
1.30
0.90
1.20
0.30
0.30
0.00
0.00
1.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
0.30
0.60
1.00
0.30
0.20
0.50
0.50
0.60
0.60
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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