CS8900A-IQZR Cirrus Logic Inc, CS8900A-IQZR Datasheet - Page 30

• Manufacturer Part Number: CS8900A-IQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

collision detection, preamble generation and
detection, and CRC generation and test. Pro-
grammable MAC features include automatic
retransmission on collision, and padding of
transmitted frames.
Figure 8 shows how the MAC engine interfac-
es to other CS8900A functions. On the host
side, it interfaces to the CS8900A’s internal
data/address/control bus. On the network
side, it interfaces to the internal Manchester
encoder/decoder (ENDEC). The primary func-
tions of the MAC are: frame encapsulation and
decapsulation; error detection and handling;
and, media access management.
3.9.2 Frame Encapsulation and Decapsu-
lation
The CS8900A’s MAC engine automatically as-
sembles transmit packets and disassembles
receive packets. It also determines if transmit
and receive frames are of legal minimum size.
30
Internal Bus
CS8900A
Figure 8. MAC Interface
Engine
802.3
Logic
MAC
LED
Direction of Transmission
alternating 1s / 0s
up to 7 bytes
preamble
SFD = Start of Frame Delimiter
DA = Destination Address
SA = Source Address
Encoder/
Decoder
PLL
SFD
&
1 byte
CIRRUS LOGIC PRODUCT DATASHEET
Figure 9. Ethernet Frame Format
6 bytes
10BASE-T
DA
& AUI
Packet
6 bytes
SA
3.9.2.1 Transmission
Once the proper number of bytes have been
transferred to the CS8900A’s memory (either
5, 381, 1021 bytes, or full frame), and provid-
ing that access to the network is permitted, the
MAC automatically transmits the 7-byte pre-
amble (1010101b...), followed by the Start-of-
Frame Delimiter (SFD, 10101011b), and then
the serialized frame data. It then transmits the
Frame Check Sequence (FCS). The data after
the SFD and before the FCS (Destination Ad-
dress, Source Address, Length, and data field)
is supplied by the host. FCS generation by the
CS8900A may be disabled by setting the In-
hibitCRC bit (Register 9, TxCMD, bit C).
Figure 9 shows the Ethernet frame format.
3.9.2.2 Reception
The MAC receives the incoming packet as a
serial stream of NRZ data from the Manches-
ter encoder/decoder. It begins by checking for
the SFD. Once the SFD is detected, the MAC
assumes all subsequent bits are frame data. It
reads the DA and compares it to the criteria
programmed into the address filter (see
Section 5.2.10 on page 87 for a description of
Address Filtering). If the DA passes the ad-
dress filter, the frame is loaded into the
CS8900A’s memory. If the BufferCRC bit
(Register 3, RxCFG, bit B) is set, the received
FCS is also loaded into memory. Once the en-
Length Field
max 1518 bytes
LLC = Logical Link Control
FCS = Frame Check Sequence (also
frame length
min 64 bytes
2 bytes
Frame
called Cyclic Redundancy Check, or CRC)
Crystal LAN™ Ethernet Controller
LLC data
Pad
4 bytes
FCS
CS8900A
DS271F5