CS8900A-IQZR Cirrus Logic Inc, CS8900A-IQZR Datasheet - Page 53

• Manufacturer Part Number: CS8900A-IQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
4.4.5 Register 0: Interrupt Status Queue
(ISQ, Read-only, Address: PacketPage base + 0120h)
The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt
information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s)
in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of
the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register
C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem-
ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See
Section 5.1 on page 78.
CS8900A
Crystal LAN™ Ethernet Controller
16coll
Dest
Rx
F
Hash Table Index (alternate RxEvent meaning if
7
F
RegContent
Extra
CRS
data
10-bit AUI Time Domain Reflectometer (TDR) counter, cleared when read
E
Hashed = 1 and RxOK = 1)
Number-of-Tx-collisions
10-bit Transmit Collision (TxCOL) counter, cleared when read
Runt
10-bit Receive Miss (RxMISS) counter, cleared when read
D
E
6
Table 16. Status and Control Register Descriptions (continued)
Polarity
EESize EL pres-
CRC
error
Reserved (register contents undefined)
Reserved (register contents undefined)
Reserved (register contents undefined)
Reserved (register contents undefined)
Reserved (register contents undefined)
Reserved (register contents undefined)
OK
C
D
5
Status and Event Bits
CIRRUS LOGIC PRODUCT DATASHEET
Interrupt Status Queue
Broad-
Rx128
cast
ent
B
EEPRO
Individ-
RxMiss TxUnder-
ual Adr
Jabber
M OK
C
4
A
RegContent
Mpresent
Window
EEPRO
Hashed
Hashed
Out-of-
10BT
run
9
B
3
SIBUSY
Rdy4Tx RxDMA
Rdy4Tx
RegNum
RxOK
RxOK
TxOK
NOW
AUI
8
LinkOK
Dribble
Dribble
Frame
INITD
TxBid
A
2
SQE
error
bits
bits
Err
7
Loss-of-
IAHash
IAHash
SWint
Active
3.3 V
CRS
6
1
9
Number
(Offset)
(012Ch)
(013Ch)
(0120h)
(0124h)
(0124h)
(0128h)
(0130h)
(0132h)
(0134h)
(0136h)
(0138h)
1C
1A
1E
10
12
14
16
18
A
C
E
0
2
4
4
6
8
Register
TxEvent
RxMISS
Eventalt
TxCOL
LineST
SelfST
BusST
0
8
Name
Event
Event
TDR
ISQ
Buf
Rx
Rx
53