LAN9215-MZP SMSC, LAN9215-MZP Datasheet
LAN9215-MZP
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LAN9215-MZP Summary of contents
Page 1
... Numerous power management modes — Wake on LAN* — Magic packet wakeup* — Wakeup indicator event signal — Link Status Change SMSC LAN9215 LAN9215 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Single chip Ethernet controller — Fully compliant with IEEE 802.3/802.3u standards — ...
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... LAN9215-MT FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) LAN9215-MZP FOR 100-BALL, LFBGA LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +70°C TEMP RANGE) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
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... Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.1 Power-On Reset (POR 3.10.2 Hardware Reset Input (nRESET 3.10.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.10.4 Soft Reset (SRST 3.10.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.11 MII Interface - External MII Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SMSC LAN9215 3 DATASHEET Revision 2.7 (03-15-10) ...
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... HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.1 Register Nomenclature and Access Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2 RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3 System Control and Status Registers Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 4 DATASHEET Datasheet SMSC LAN9215 ...
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... Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.5.13 PHY Special Control/Status 120 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 121 SMSC LAN9215 5 DATASHEET Revision 2.7 (03-15-10) ...
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... Worst Case Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.1 100-TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.2 100-LFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 6 DATASHEET Datasheet SMSC LAN9215 ...
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... Figure 6.7 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 6.8 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 8.1 100 Pin TQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 8.2 100 Ball LFBGA Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 8.3 100 Ball LFBGA Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SMSC LAN9215 7 DATASHEET Revision 2.7 (03-15-10) ...
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... Table 5.6 MAC CSR Register Map 101 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 5.8 LAN9215 PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 6 ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SMSC LAN9215 9 DATASHEET Revision 2.7 (03-15-10) ...
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... The LAN9215 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9215 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Compatibility with First-generation LAN9118 Family Devices The LAN9215 is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers written for these products will work with the LAN9215. However, in order to support HP Auto-MDIX, other components such as the magnetics and the passive components around the magnetics need to change, and supporting these changes does require a minor PCB change. A reference design for the LAN9215 will be available on SMSC’ ...
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... On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN9215. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.The Ethernet MAC can also communicate with an external PHY ...
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... Serial EEPROM Interface A serial EEPROM interface is included in the LAN9215. The serial EEPROM is optional and can be programmed with the LAN9215 MAC address. The LAN9215 can optionally load the MAC address automatically after power-on reset, hardware reset, or soft reset. ...
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... The LAN9215 can be interfaced to either Big-Endian or Little-Endian processors. 1.13 External MII Interface The LAN9215 also supports the ability to interface to an external PHY device. This interface is compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the MII interface and associated signals, please refer to Switching," ...
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... GND_IO 96 VDD_IO 97 GPIO0/nLED1** 98 GPIO1/nLED2** 99 GPIO2/nLED3** 100 **Denotes a multifunction pin NOTE 1: When HP Auto-MDIX is activated, the TPO+/- pins function as TPI+/- and vice-versa. Figure 2.1 100-TQFP Pin Configuration (Top View) SMSC LAN9215 SMSC LAN9215 100 PIN TQFP 15 DATASHEET 50 D10 49 D11 48 VDD_IO 47 GND_IO 46 D12 ...
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... GND GND COL TXD2 TX_CLK D14 TXD3 TXD1 TXD0 D15 DATASHEET Datasheet TPI- TPO+ TPO- FIFO_SEL B VDD_IO VDD_A RXD0 SPEED_SEL C VDD_IO AMDIX_EN IRQ D VDD_CORE VDD_IO NC E PME EECLK F EECS EEDIO VDD_CORE VDD_IO D4 K VDD_IO VDD_IO D11 D13 D12 D10 SMSC LAN9215 ...
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... LAN9215 when reduced power state Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9215 when reduced power state. O8/OD8 1 Programmable Interrupt request. Programmable polarity, source and buffer types. ...
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... GPO signal RX_DV/RX_CLK monitor, the EECS pin is deasserted never unintentionally access the serial EEPROM. This signal cannot function as a general-purpose input. Note: When the EEPROM interface is not used, the EECLK pin must be left unconnected. 18 DATASHEET Datasheet DESCRIPTION SMSC LAN9215 ...
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... If nRESET is left unconnected, the LAN9215 will rely on its internal power-on reset circuitry. Note: O8/OD8 1 When programmed to do so, is asserted when the LAN9215 detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note Enables Auto-MDIX ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9215 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then ...
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... VSS_PLL Reference Power VDD_REF Reference Ground VSS_REF Ground GND Note 2.1 Please refer to the SMSC application note ”AN14.9 - “Migrating from LAN9115 to the LAN9215” for additional details. NAME SYMBOL Transmit Clock: TX_CLK Transmit Data [3:0] TXD[3:0] Transmit Enable TX_EN Receive Clock ...
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... O8 1 Management Data Clock: When SMI_SEL = 1, this pin is the MII management data clock. (PD) When SMI_SEL=0, this pin is driven low. Note: See "HW_CFG—Hardware Configuration Register" SMI_SEL. 22 DATASHEET Datasheet DESCRIPTION Section 5.3.9, for more information on Section 5.3.9, for more information on SMSC LAN9215 ...
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... GND_IO 44 20 VDD_IO 45 21 TX_EN 46 22 RXD1 47 23 RXD2 48 24 RXD3 49 25 RX_ER 50 SMSC LAN9215 PIN PIN NAME NUM PIN NAME RX_CLK 51 D9 GND_IO 52 D8 VDD_IO 53 D7 RX_DV 54 GND_IO MDIO 55 VDD_IO MDC 56 D6 CRS 57 D5 COL 58 D4 GND_IO 59 D3 VDD_IO 60 GND_IO ...
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... EEDIO K11 D6 24 DATASHEET Datasheet PIN NUM PIN NAME K12 D5 L1 RXD3 L2 RX_ER L3 MDIO L4 VDD_IO L5 COL L6 TXD2 L7 TX_CLK L8 D14 L9 VDD_IO L10 D11 L11 D8 L12 D7 M1 RX_CLK M2 RX_DV M3 MDC M4 CRS M5 TXD3 M6 TXD1 M7 TXD0 M8 D15 M9 D13 M10 D12 M11 D10 M12 D9 SMSC LAN9215 ...
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... OD8 Output 8mA symmetrical drive O8 50uA (typical) internal pull-up PU 50uA (typical) internal pull-down PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK SMSC LAN9215 Table 2.9 Buffer Types DESCRIPTION 25 DATASHEET Revision 2.7 (03-15-10) ...
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... Generation of control frames Interface to the internal PHYand optional external PHY. The transmit and receive data paths are separate within the LAN9215 from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet The LAN9215 can store up to 250 Ethernet packets utilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms of allocation. This depth of buffer storage minimizes or eliminates receive overruns. ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9215 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9215 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9215 packet filter function performs an imperfect address filtering against the hash table ...
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... Upon detection, the Wake-Up Frame Received bit (WUFR) in the WUCSR is set. When the host clears the WUEN bit the LAN9215 will resume normal receive operation. Before putting the MAC into the wake-up frame detection state, the host must provide the detection logic with a list of sample frames and their corresponding byte masks ...
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... Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. SMSC LAN9215 Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask ...
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... MAC examines receive data for a Magic Packet. The LAN9215 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9215 is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. ...
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... EEPROM is not detected the responsibility of the host LAN Driver to set the IEEE addresses. The LAN9215 EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation ...
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... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9215 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support EEPROM Read Idle Write Data Register Write Command Register Read Command Register Section 5.3.23, "E2P_CMD – EEPROM Command Register," DATASHEET Datasheet Idle Write Command Register Read Command Register Busy Bit = 0 Read Data Register SMSC LAN9215 ...
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... ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) SMSC LAN9215 Figure 3.3 EEPROM ERASE Cycle 0 0 ...
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... Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Figure 3.5 EEPROM EWDS Cycle Figure 3.6 EEPROM EWEN Cycle 38 DATASHEET Datasheet t CSL t CSL SMSC LAN9215 ...
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... E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Table 3.8, "Required EECLK each EEPROM operation. SMSC LAN9215 Figure 3.7 EEPROM READ Cycle Figure 3 ...
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... Refer to Section 6.9, "EEPROM Timing," on page 131 3.9 Power Management The LAN9215 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.9.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management States,” ...
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... In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_CTRL register can be read to determine which LAN9215 device is driving the PME signal. When the LAN9215 power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the LAN9215 to the D0 state. Components,” on page 134 page 134, shows the power consumption values for each power state ...
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... A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9215 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9215 can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.12 After a POR, nRESET or SRST, the LAN9215 will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC ...
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... Resume Reset Timing After issuing a write to the BYTE_TEST register to wake the LAN9215 from a power-down state, the READY bit in PMT_CTRL will assert (set High) within 2ms. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If the software driver polls this bit and it is not set within 100ms, then an error condition occurred ...
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... The LAN9215 Receiver must be halted. The halting of the LAN9215 receiver must be complete. The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks to the LAN9215 internal logic for both the internal PHY, and the external MII interface. The host must wait a period of time not less than 5 cycles of the slowest operating clock before executing the next step in this procedure ...
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... Enable the LAN9215 transmitter. Enable the LAN9215 receiver. The process is complete. The LAN9215 is now operational using the newly selected MII device. The above procedure must be repeated each time the MII port is switched. The procedure is identical when switching from internal PHY to external MII, or vice-versa. ...
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... Clocks Halted? YES Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 8 EXT_PHY_SEL to Desired MII Port 9 PHY_CLK_SEL to Desired MII Port Figure 3.11 MII Switching Procedure 48 DATASHEET Datasheet Set Set Clocks NO Running YES Enable RX Enable TX Complete SMSC LAN9215 ...
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... Buffer End Alignment field specified in each TX command. The host can instruct the LAN9215 to issue an interrupt when the buffer has been fully loaded into the TX FIFO contained in the LAN9215 and transmitted. This feature is enabled through the TX command ‘ ...
Page 50
... TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32- bit values that are used by the LAN9215 in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure ...
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... TX data FIFO usage. Please refer to "Calculating Actual TX Data FIFO Usage," on page 55 actual TX data FIFO usage. Note 3.15 The LAN9215 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. ...
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... This value, along with the Buffer End Alignment field, is read and checked by the LAN9215 and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9215 of the cumulative buffer sizes for a given packet. ...
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... The first buffer of any transmit packet can be any length Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit packet can be any length SMSC LAN9215 Table 3.12 TX Command 'B' Format DESCRIPTION Table 3.13, "TX DATA Start Table 3 ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9215. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN9215 DESCRIPTION 55 DATASHEET Revision 2.7 (03-15-10) ...
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... Figure 3.14, "TX Example 1" how data is passed to the TX data FIFO. Note 3.16 The LAN9215 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. atomic 16-bit transactions. Ethernet Controller 31 TX Com m and 'A' Buffer End Alignment = 1 Data Start Offset = 7 ...
Page 57
... Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9215 illustrates the TX command structure for this example, and also shows Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3 ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9215 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9215 is operating in a system that always performs multi-DWORD bursts ...
Page 59
... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.16 Host Receive Routine Using Interrupts Figure 3.17 Host Receive Routine with Polling SMSC LAN9215 init Idle RX Interrupt Read RX ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9215 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
Page 61
... RX status FIFO, to ascertain the data size and any error conditions. Host Read Order Last Note 3.17 The LAN9215 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. 3.13.3 RX Status Format ...
Page 62
... A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support DESCRIPTION 62 DATASHEET Datasheet SMSC LAN9215 ...
Page 63
... F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is th bypassed the 5 transmit data bit is equivalent to TX_ER. SMSC LAN9215 100M PLL 4B/5B 25MHz MII ...
Page 64
... Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID 64 DATASHEET Datasheet TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN9215 ...
Page 65
... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN9215 Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 65 ...
Page 66
... Decoder 125 Mbps Serial recovery, Equalizer MLT-3 and BLW Correction Magnetics RJ45 MLT-3 MLT-3 6 bit Data Figure 4.2 Receive Data Path Figure 4.2. Detailed descriptions are given below. 66 DATASHEET Datasheet Descrambler 25MHz by 5 bits and SIPO DSP: Timing CAT-5 SMSC LAN9215 ...
Page 67
... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted SMSC LAN9215 67 DATASHEET ...
Page 68
... Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 68 DATASHEET Datasheet SMSC LAN9215 ...
Page 69
... Auto-negotiation will also re-start if not all of the required FLP bursts are received. Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new SMSC LAN9215 69 DATASHEET ...
Page 70
... Parallel Detection If the LAN9215 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
Page 71
... Mbps Note 4.1 The LAN9215 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, the internal CRS stays low and does not indicate carrier detection ...
Page 72
... The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9215 is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support ...
Page 73
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet Chapter 5 Register Description The following section describes all LAN9215 registers and data ports. Note: The LAN9215 host bus interface supports 16-bit bus transfers; internally, all data paths are 32- bits wide. Figure 5.1 transactions. ...
Page 74
... LAN9215 registers accordingly. 5.2 RX and TX FIFO Ports The LAN9215 contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data ...
Page 75
... ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED SMSC LAN9215 Map", lists the registers that are directly addressable by the host Table 5.1 Direct Address Register Map CONTROL AND STATUS REGISTERS REGISTER NAME Chip ID and Revision. Main Interrupt Configuration Interrupt Status ...
Page 76
... This bit has no effect on any internal interrupt status bits. 7-5 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 50h Size: DESCRIPTION 54h Size: DESCRIPTION 76 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 115Ah RO 0000h 32 bits TYPE DEFAULT R R SMSC LAN9215 ...
Page 77
... IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function as an open-drain buffer for use in a Wired-Or Interrupt configuration. When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. SMSC LAN9215 DESCRIPTION 77 DATASHEET TYPE ...
Page 78
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9215. The LAN9215 will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 79
... FIFO is full Status FIFO Level Interrupt (RSFL). Generated when the RX Status FIFO reaches the programmed level. 2-0 GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. SMSC LAN9215 DESCRIPTION 79 DATASHEET TYPE DEFAULT RO ...
Page 80
... Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 5Ch Size: DESCRIPTION 80 DATASHEET Datasheet 32 bits TYPE DEFAULT R R/W 0 R R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R R/W 0 R/W 0 R/W 0 R R/W 0 R/W 0 R/W 000 SMSC LAN9215 ...
Page 81
... RX Status Level. The value in this field sets the level, in number of DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be generated. When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. SMSC LAN9215 64h Size: DESCRIPTION ...
Page 82
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9215 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 83
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9215 Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero ...
Page 84
... DESCRIPTION Section 5.3.9.1, "Allowable settings for for more information. Section 3.11, for details. 84 DATASHEET Datasheet 32 bits Section and Section 3.13.4, "Stopping and TYPE DEFAULT AMDIX Strap Pin RO - R R/W 00b R/W 0 SMSC LAN9215 ...
Page 85
... The internal RX_CLK and TX_CLK signals must be running for a proper software reset. Please refer to Section 6.8, "Reset Timing," on page 130 The LAN9215 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. SMSC LAN9215 DESCRIPTION Section 3 ...
Page 86
... DATASHEET Datasheet RX STATUS FIFO SIZE (BYTES) SIZE (BYTES) 13440 896 12480 832 11520 768 10560 704 9600 640 8640 576 7680 512 6720 448 5760 384 4800 320 3840 256 2880 192 1920 128 SMSC LAN9215 ...
Page 87
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9215 moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 88
... RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9215 Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. 15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO ...
Page 89
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9215 Note: The LAN9215 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS 31:14 ...
Page 90
... Device Ready (READY). When set, this bit indicates that LAN9215 is ready to be accessed. This register can be read when LAN9215 is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9215 has stabilized and is fully alive ...
Page 91
... GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as output. When cleared the GPIO is enabled as an input. GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 7:5 Reserved SMSC LAN9215 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 91 DATASHEET ...
Page 92
... Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 TX_EN TX_EN TX_CLK 8Ch Size: DESCRIPTION 92 DATASHEET Datasheet TYPE DEFAULT R/W 00 R/W 000 EECLK FUNCTION EECLK GPO4 Reserved RX_DV Reserved GPO4 RX_DV RX_CLK 32 bits TYPE DEFAULT R/W FFFFh SMSC LAN9215 ...
Page 93
... This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN9215. The LAN9215 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 94
... An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION 94 DATASHEET Datasheet 32 bits TYPE DEFAULT bits TYPE DEFAULT RC 00000000h SMSC LAN9215 ...
Page 95
... MAC_CSR_DATA – MAC CSR Synchronizer Data Register Offset: This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s BITS 31-0 MAC CSR Data. Value read from or written to the MAC CSR’s. SMSC LAN9215 A4h Size: DESCRIPTION A8h Size: DESCRIPTION ...
Page 96
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9215 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 ...
Page 97
... Datasheet BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9215 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9215 is operating in full-duplex mode. ...
Page 98
... After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support B0h Size: DESCRIPTION 98 DATASHEET Datasheet 32 bits TYPE DEFAULT SC 0 SMSC LAN9215 ...
Page 99
... MAC address from the EEPROM value of 0xA5 is not found in the first address of the EEPROM, the EEPROM is assumed to be un- programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. SMSC LAN9215 DESCRIPTION [28] OPERATION 0 0 ...
Page 100
... EEPROM Data. Value read from or written to the EEPROM. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 100 DATASHEET Datasheet TYPE DEFAULT R/WC 0 R/WC - R/W 00h 32 bits TYPE DEFAULT RO - R/W 00h SMSC LAN9215 ...
Page 101
... FLOW 9 VLAN1 A VLAN2 B WUFF C WUCSR SMSC LAN9215 Map", shown below, lists the MAC registers that are Table 5.6 MAC CSR Register Map REGISTER NAME MAC Control Register MAC Address High MAC Address Low Multicast Hash Table High Multicast Hash Table Low ...
Page 102
... Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 1 Attribute: 00040000h Size: DESCRIPTION 102 DATASHEET Datasheet R/W 32 bits SMSC LAN9215 ...
Page 103
... Datasheet BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9215 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 104
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9215 device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. ...
Page 105
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9215 device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 106
... BITS 31-0 Lower 32 bits of the 64-bit Hash Table Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 106 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN9215 ...
Page 107
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9215 to read or write any of the MII PHY registers. ...
Page 108
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9215 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 109
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN9215 9 Attribute: 00000000h ...
Page 110
... Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support B Attribute: 00000000h Size: DESCRIPTION C Attribute: 00000000h Size: DESCRIPTION 110 DATASHEET Datasheet WO 32 bits R/W 32 bits SMSC LAN9215 ...
Page 111
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9215 PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 112
... The default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 0 Size: DESCRIPTION 112 DATASHEET Datasheet 16-bits TYPE DEFAULT RW/ See Note 5.1 RW See Note 5 RW/ SMSC LAN9215 ...
Page 113
... Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. 5.5.3 PHY Identifier 1 Index (In Decimal): BITS 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN9215 1 Size: DESCRIPTION 2 Size: DESCRIPTION 113 DATASHEET ...
Page 114
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5.2) 114 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0xC0C3h RO RO 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.3 R/W 1 R/W See Note 5.3 R/W See Note 5.3 R/W 00001 SMSC LAN9215 ...
Page 115
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9215 5 Size: DESCRIPTION 115 DATASHEET 16-bits TYPE DEFAULT ...
Page 116
... The default value of this bit will vary dependant on the current link state of the line. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 6 Size: DESCRIPTION 17 Size: DESCRIPTION 116 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT See Note 5 SMSC LAN9215 ...
Page 117
... Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9215 in this mode. 111 All capable. Auto-negotiation enabled. Note 5.5 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto- negotiated speed and duplex. ...
Page 118
... XPOL: Polarity state of the 10Base- Normal polarity 1 - Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 27 Size: DESCRIPTION 118 DATASHEET Datasheet 16-bits MODE DEFAULT RW, 0 NASR XXXXb SMSC LAN9215 ...
Page 119
... The default value of this bit will vary dependant on the current link state of the line. 5.5.12 Interrupt Mask Index (In Decimal): BITS 15-8 Reserved. Write as 0; ignore on read. 7-0 Mask Bits interrupt source is enabled 0 = interrupt source is masked SMSC LAN9215 29 Size: DESCRIPTION 30 Size: DESCRIPTION 119 DATASHEET ...
Page 120
... Reserved. Write as 0; ignore on Read Note 5.7 See Table 2.2, “Default Ethernet Settings,” on page Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support 31 Size: DESCRIPTION 120 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 000b 0000010b RO See Note 5.7 RO 00b 17, for default settings. SMSC LAN9215 ...
Page 121
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9215 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 122
... MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 165 165 165 0 165 165 165 165 165 0 165 330 165 165 165 165 330 0 165 165 165 165 165 122 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 165NS) CYCLE SMSC LAN9215 ...
Page 123
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9215, and the subsequent indication of the expected change in the control register values. ...
Page 124
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Figure 6.1 PIO Read Cycle Timing Table 6.3 PIO Read Timing and t must be extended using wait states to meet the t csl 124 DATASHEET Datasheet MIN TYP MAX UNITS 165 133 minimum. cycle SMSC LAN9215 ...
Page 125
... Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9215 Figure 6.2 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing ...
Page 126
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9215 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215 ...
Page 127
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9215 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215 ...
Page 128
... PIO Writes PIO writes are used for all LAN9215 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] nCS, nWR Data Bus Note: The “ ...
Page 129
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9215 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215 ...
Page 130
... Output Drive after nRESET rising Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support T6.1 T6.2 T6.3 T6.4 Figure 6.7 Reset Timing Table 6.9 Reset Timing MIN TYP MAX 200 200 10 16 130 DATASHEET Datasheet UNITS NOTES SMSC LAN9215 ...
Page 131
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9215: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK ...
Page 132
... Note: Apply and remove power to all power supply pins simultaneously, including the Ethernet magnetics. Do not apply power to individual supply pins without the others. **Proper operation of the LAN9215 is guaranteed only within the ranges specified in this section. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support (Note 7 ...
Page 133
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9215 in various modes of operation. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD:................................................................................................................................... +3.30V Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements ...
Page 134
... This section provides typical power consumption values for a complete Ethernet interface based on the LAN9215, including the power dissipated by the magnetics and other passive components. Please refer to the SMSC application note AN14.9 - “Migrating from LAN9115 to the LAN9215”, that can be found on SMSC’s web site www.smsc.com, which contains additional details on magnetics and other components used ...
Page 135
... I/O Supply Current +3.3V Analog Supply Current Reference Supply Current Note: Above values do not include the supply current for the magnetics. Based on the recommended implementation, the maximum supply current needed for the magnetics is 108mA. SMSC LAN9215 SUPPLY NAME MAX VREG 69 ...
Page 136
... DC Electrical Specifications This section details the DC electrical specifications of the LAN9215 I/O buffers. The electrical specifications in this section are valid over the voltage range and the temperature range specified in Section 7.2, "Operating PARAMETER SYMBOL I Type Input Buffer Low Input Level V ILI ...
Page 137
... Measured differentially. Table 7.6 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. SMSC LAN9215 MIN TYP MAX -0.3 0.5 1.4 3.6 input leakage for the entire device. This value should be divided by IN MAX to calculate per-pin leakage ...
Page 138
... Clock Circuit The LAN9215 can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9215 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 139
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN9215 MAX REMARKS 1.60 Overall Package Height 0 ...
Page 140
... The A1 corner identifier may vary, but is always located within the zone indicated. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support MAX REMARKS 1.70 Overall Package Height ~ Standoff 1.36 Package Body Thickness 10.10 Overall Package Size 0.50 Ball Diameter Ball Pitch 0.20 Coplanarity 140 DATASHEET Datasheet SMSC LAN9215 ...
Page 141
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support Datasheet Figure 8.3 100 Ball LFBGA Recommended PCB Land Pattern SMSC LAN9215 141 DATASHEET Revision 2.7 (03-15-10) ...
Page 142
... Also added note stating “When both symmetric PAUSE and asymmetric PAUSE support are advertised, the device will only be configured to, at most, one of the two settings upon auto-negotiation completion.” 142 DATASHEET Datasheet CORRECTION SMSC LAN9215 ...
Page 143
... Outline," on page ordering code EECLK pin description in Chapter 2 Pin Description and Configurationon page 15 SMSC LAN9215 Added note: “When wake-up frame detection is enabled via the WUEN bit of the and Section 5.4.1, up Control and Status up frame will wake-up the device despite the state of the Disable Broadcast Frame (BCAST) bit in the MAC_CR— ...