LAN91C100FD-SS SMSC, LAN91C100FD-SS Datasheet - Page 32

• Manufacturer Part Number: LAN91C100FD-SS
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C100FD-SS

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
COMMAND SEQUENCING
BANK 2
Revision 1.0 (09-22-08)
Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software
compatibility with the LAN91C92 and future devices. They should be zero for all other commands.
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports
register before issuing the command.
MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number
has memory allocated to it.
FAILED
OFFSET
OFFSET
A second allocate command (command 1) should not be issued until the present one has completed.
Completion is determined by reading the FAILED bit of the allocation result register or through the
allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being
processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the
contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3
should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still
processing a release command. When clear, MMU has already completed last release command. BUSY
and FAILED bits are set upon the trailing edge of command.
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is
accessible through the TX area. Some MMU commands use the number stored in this register as the
packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
This register is updated upon an ALLOCATE MEMORY MMU command.
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only
cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For
polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is
synchronized to the read operation. Sequence:
1.
2.
3.
0
0
1
2
3
Allocate Command
Poll ALLOC_INT bit until set
Read Allocation Result Register
ALLOCATION RESULT REGISTER
0
0
0
0
PACKET NUMBER REGISTER
0
0
NAME
NAME
DATASHEET
0
0
ALLOCATED PACKET NUMBER
PACKET NUMBER AT TX AREA
Page 32
0
0
READ/WRITE
READ ONLY
FEAST Fast Ethernet Controller with Full Duplex Capability
TYPE
TYPE
0
0
0
0
SMSC LAN91C100FD Rev. D
SYMBOL
SYMBOL
PNR
ARR
0
0