LAN8720AI-CP-TR SMSC, LAN8720AI-CP-TR Datasheet

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LAN8720AI-CP-TR

Manufacturer Part Number
LAN8720AI-CP-TR
Description
Ethernet ICs 10/100 Ethernet XCVR w/HP AutoMDIXSupport
Manufacturer
SMSC
Datasheet

Specifications of LAN8720AI-CP-TR

Product
Ethernet Transceivers
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Highlights
Target Applications
SMSC LAN8720A/LAN8720Ai
PRODUCT FEATURES
Single-Chip Ethernet Physical Layer Transceiver
Comprehensive flexPWR
HP Auto-MDIX support
Miniature 24-pin QFN lead-free RoHS compliant
Set-Top Boxes
Networked Printers and Servers
Test Instrumentation
LAN on Motherboard
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems/Routers
DSL Modems/Routers
Digital Video Recorders
IP and Video Phones
Wireless Access Points
Digital Televisions
Digital Media Adaptors/Servers
Gaming Consoles
POE Applications
(PHY)
— Flexible Power Management Architecture
— LVCMOS Variable I/O voltage range: +1.6V to +3.6V
— Integrated 1.2V regulator
package (4 x 4 x 0.85mm height).
(Refer to SMSC Application Note 17.18)
Small Footprint RMII 10/100 Ethernet
Transceiver with HP Auto-MDIX Support
®
Technology
DATASHEET
Key Benefits
High-Performance 10/100 Ethernet Transceiver
Power and I/Os
Additional Features
Packaging
Environmental
— Compliant with IEEE802.3/802.3u (Fast Ethernet)
— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
— Loop-back modes
— Auto-negotiation
— Automatic polarity detection and correction
— Link status change wake-up detection
— Vendor specific register functions
— Supports the reduced pin count RMII interface
— Various low power modes
— Integrated power-on reset circuit
— Two status LED outputs
— Latch-Up Performance Exceeds 150mA per EIA/JESD
— May be used with a single 3.3V supply
— Ability to use a low cost 25Mhz crystal for reduced BOM
— 24-pin QFN (4x4 mm) Lead-Free RoHS Compliant
— Extended commercial temperature range
— Industrial temperature range version available
LAN8720A/LAN8720Ai
78, Class II
package with RMII
(0°C to +85°C)
(-40°C to +85°C)
Revision 1.2 (11-10-10)
Datasheet

Related parts for LAN8720AI-CP-TR

LAN8720AI-CP-TR Summary of contents

Page 1

... Wireless Access Points Digital Televisions Digital Media Adaptors/Servers Gaming Consoles POE Applications (Refer to SMSC Application Note 17.18) SMSC LAN8720A/LAN8720Ai LAN8720A/LAN8720Ai Key Benefits High-Performance 10/100 Ethernet Transceiver — Compliant with IEEE802.3/802.3u (Fast Ethernet) — Compliant with ISO 802-3/IEEE 802.3 (10BASE-T) — Loop-back modes — ...

Page 2

... LAN8720A-CP-TR for 24-pin, QFN lead-free RoHS compliant package (0 to +85°C temp) LAN8720Ai-CP-TR for 24-pin, QFN lead-free RoHS compliant package (-40 to +85°C temp) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...

Page 3

... Power Supply Diagram (1.2V Supplied by External Source 3.9.4 Twisted-Pair Interface Diagram (Single Power Supply 3.9.5 Twisted-Pair Interface Diagram (Dual Power Supplies Chapter 4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1 Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMSC LAN8720A/LAN8720Ai 3 DATASHEET Revision 1.2 (11-10-10) ...

Page 4

... Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.4 RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.5 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Chapter 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Chapter 7 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 4 DATASHEET Datasheet SMSC LAN8720A/LAN8720Ai ...

Page 5

... Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 5.4 RMII Timing (REF_CLK Out Mode Figure 5.5 RMII Timing (REF_CLK In Mode Figure 5.6 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SMSC LAN8720A/LAN8720Ai 5 DATASHEET Revision 1.2 (11-10-10) ...

Page 6

... Table 5.10 RMII Timing Values (REF_CLK In Mode Table 5.11 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 5.12 SMI Timing Values Table 5.13 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 6 DATASHEET Datasheet SMSC LAN8720A/LAN8720Ai ...

Page 7

... The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation. The LAN8720A/LAN8720Ai is available in both extended commercial and industrial temperature range versions. A typical system application is shown in SMSC LAN8720A/LAN8720Ai 8-bits First In First Out buffer ...

Page 8

... Data Recovery Equalizer 100M PLL Receiver Squeltch & Filters 10M PLL Figure 1.2 Architectural Overview 8 DATASHEET Datasheet RJ45 HP Auto-MDIX TXP/TXN RXP/RXN MDIX Control XTAL1/CLKIN PLL XTAL2 Interrupt nINT Generator LED1 LEDs LED2 RBIAS Central Bias PHY Address PHYAD0 Latches SMSC LAN8720A/LAN8720Ai ...

Page 9

... Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in SMSC LAN8720A/LAN8720Ai SMSC LAN8720A/LAN8720Ai 24 PIN QFN ...

Page 10

... Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. for more information on Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. for more information on Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 31 for additional information. SMSC LAN8720A/LAN8720Ai ...

Page 11

... Section 3.7, "Configuration Straps," on page 31 NUM PINS NAME SYMBOL LED 1 Regulator Off Configuration Strap 1 SMSC LAN8720A/LAN8720Ai Table 2.1 RMII Signals (continued) BUFFER TYPE CRS_DV VO8 This signal is asserted to indicate the receive medium is non-idle. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte (10101011) is received ...

Page 12

... Transmit/Receive Negative Channel 1 12 DATASHEET Datasheet DESCRIPTION Refer to Section 3.8.1, "LEDs," on page 37 for additional LED information. for more information on Refer to See Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection," on page 37 for additional information. for additional information. DESCRIPTION DESCRIPTION SMSC LAN8720A/LAN8720Ai ...

Page 13

... External Clock Input External 1 Crystal Output External 1 Reset Interrupt Output 1 Reference REFCLKO Clock Output SMSC LAN8720A/LAN8720Ai Table 2.4 Ethernet Pins (continued) BUFFER TYPE RXP AIO Transmit/Receive Positive Channel 2 RXN AIO Transmit/Receive Negative Channel 2 Table 2.5 Miscellaneous Pins BUFFER TYPE XTAL1 ICLK ...

Page 14

... Analog Port Power to Channel 1 Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. VDD2A P +3.3V Analog Port Power to Channel 2 and the internal regulator. Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. VSS P Common ground. This exposed pad must be connected to the ground plane with a via array. 14 ...

Page 15

... Table 2.8 24-QFN Package Pin Assignments PIN NUM PIN NAME 1 VDD2A 2 LED2/nINTSEL 3 LED1/REGOFF 4 XTAL2 5 XTAL1/CLKIN 6 VDDCR 7 RXD1/MODE1 8 RXD0/MODE0 9 VDDIO 10 RXER/PHYAD0 11 CRS_DV/MODE2 12 MDIO SMSC LAN8720A/LAN8720Ai PIN NUM PIN NAME 13 14 nINT/REFCLKO DATASHEET MDC nRST TXEN TXD0 TXD1 VDD1A TXN TXP RXN RXP RBIAS Revision 1 ...

Page 16

... Sink and source capabilities are dependant on the VDDIO voltage. Refer to "Absolute Maximum Ratings*," on page 63 Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 2.9 Buffer Types DESCRIPTION Section 5.1, "Absolute Maximum Ratings*," on for additional information. 16 DATASHEET Datasheet Section 5.1, SMSC LAN8720A/LAN8720Ai ...

Page 17

... The MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50MHz data. SMSC LAN8720A/LAN8720Ai Figure 3.1. Each major block is explained in the ...

Page 18

... Sent for falling TXEN Sent for falling TXEN Sent for rising TXER INVALID 18 DATASHEET Datasheet Table 3.1. Each 4-bit data-nibble TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN8720A/LAN8720Ai ...

Page 19

... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX transmitter. SMSC LAN8720A/LAN8720Ai Table 3.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 19 ...

Page 20

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 3.2. Each major block is explained in the PLL 25MHz by 4 bits 4B/5B RMII Decoder 125 Mbps Serial DSP: Timing MLT-3 recovery, Equalizer and BLW Correction MLT-3 MLT-3 RJ45 6 bit Data 20 DATASHEET Datasheet 25MHz by Descrambler 5 bits and SIPO CAT-5 SMSC LAN8720A/LAN8720Ai ...

Page 21

... SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that the Valid Data signal is not yet asserted when the bad SSD error occurs. SMSC LAN8720A/LAN8720Ai 5 5 ...

Page 22

... The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs. Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 22 DATASHEET Datasheet SMSC LAN8720A/LAN8720Ai ...

Page 23

... Special logic is used to detect the jabber state and abort the transmission to the line within 45ms. Once TXEN is deasserted, the logic resets the jabber condition. As shown in Section 4.2.2, "Basic Status Register," on page jabber condition was detected. SMSC LAN8720A/LAN8720Ai XPOL bit of the Special Control/Status Indications 50, the ...

Page 24

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support bits of the PHY Special Control/Status Register. The auto-negotiation protocol is a purely physical layer bit of the Basic Control Register Register. 24 DATASHEET Datasheet Register, as well as in the Auto Auto Negotiation Advertisement Auto SMSC LAN8720A/LAN8720Ai ...

Page 25

... Parallel Detection If the LAN8720A/LAN8720Ai is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half duplex per the IEEE standard. ...

Page 26

... RXN RXN 6 6 Not Used Not Used 7 7 Not Used Not Used DATASHEET Datasheet Figure 3.4, the device’s Auto-MDIX bit in the Special Control/Status signaling TXP 1 TXN 2 RXP 3 Not Used 4 Not Used 5 RXN 6 Not Used 7 Not Used 8 Cross-Over Cable SMSC LAN8720A/LAN8720Ai ...

Page 27

... However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK. SMSC LAN8720A/LAN8720Ai 27 DATASHEET Revision 1.2 (11-10-10) ...

Page 28

... The timing relationships of the MDIO signals are 74. Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address Data To Phy 28 DATASHEET Datasheet Chapter 4, "Register Descriptions," ... ... D1 D15 D14 D0 Turn Data Around Data From Phy ... ... D15 D14 D1 D0 Turn Data Around SMSC LAN8720A/LAN8720Ai ...

Page 29

... Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine. Note: The ENERGYON signal acquisition process, therefore the SMSC LAN8720A/LAN8720Ai Table 3.2 Interrupt Management Table EVENT TO INTERRUPT SOURCE ASSERT nINT 17.1 ENERGYON Rising 17 ...

Page 30

... Interrupt Mask Register will also read ENERGYON and INT7 will clear within SMSC LAN8720A/LAN8720Ai to ...

Page 31

... The device’s mode may be configured using the hardware configuration straps as summarized in Table 3.4. The user may configure the transceiver mode by writing the SMI registers. SMSC LAN8720A/LAN8720Ai Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on Special Modes Register. The PHYAD0 hardware configuration strap is ...

Page 32

... CRS_DV/MODE2 for additional information on the relation between 32 DATASHEET Datasheet DEFAULT REGISTER BIT VALUES REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] 0000 N/A 0001 N/A 1000 N/A 1001 N/A 1100 0100 1100 0100 N/A N/A X10X 1111 Table Section 3.8.1.1, "REGOFF and SMSC LAN8720A/LAN8720Ai 3.5. ...

Page 33

... Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper consideration must also be given to the LED polarity. Refer to LED2 Polarity Selection," on page 37 nINTSEL and the LED2 polarity. SMSC LAN8720A/LAN8720Ai , then the internal regulator is disabled and IH , then the internal +1.2V regulator will turn IL Table 3 ...

Page 34

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 3.7. LAN8720A/LAN8720Ai 10/100 PHY 24-QFN RMII MDIO MDC nINT TXD[1:0] 2 TXEN RXD[1:0] 2 CRS_DV RXER XTAL1/CLKIN LED[2:1] 2 XTAL2 nRST 34 DATASHEET Datasheet Mag RJ45 TXP TXN RXP RXN All RMII signals are synchronous to the supplied clock rd overtone Figure 3.8. SMSC LAN8720A/LAN8720Ai ...

Page 35

... In some system architectures, a 25MHz clock source is available. The device can be used to generate the REF_CLK to the MAC as shown in only a 25MHz clock can be used (clock cannot be 50MHz). Similar to the 25MHz crystal mode, the nINT function is disabled. SMSC LAN8720A/LAN8720Ai LAN8720A/LAN8720Ai MDIO 10/100 PHY MDC ...

Page 36

... Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720A/LAN8720Ai 10/100 PHY 24-QFN RMII MDIO MDC TXD[1:0] TXP TXEN TXN RXD[1:0] RXP RXN CRS_DV RXER REFCLKO XTAL1/CLKIN LED[2:1] XTAL2 nRST 36 DATASHEET Datasheet Mag RJ45 25MHz Clock SMSC LAN8720A/LAN8720Ai ...

Page 37

... The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically change polarity based on the presence of an external pull-down resistor. If the LED2 pin is pulled high to VDD2A to select a logical high for nINTSEL, then the LED2 output will be active low. If the LED2 SMSC LAN8720A/LAN8720Ai and Section 3.8.1.1, "REGOFF and LED1 Polarity Selection," ...

Page 38

... When the Power Down EDPWRDOWN ENERGYON bit of the Mode Control/Status Register 38 DATASHEET Datasheet LED2/nINTSEL ~270 ohms for additional for additional information. bit of the Basic Control Register. In this bit is cleared, the transceiver bit of the Mode Control/Status is low, the transceiver is SMSC LAN8720A/LAN8720Ai ...

Page 39

... IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by some non-IDLE symbol. SMSC LAN8720A/LAN8720Ai bit of the Mode Control/Status Register to “1”. In isolation mode, the transceiver does not respond to the TXD, Section 5.5.3, " ...

Page 40

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and to drive the LINK LED (LED1). Figure 3.12. The near-end loopback mode is enabled by Basic Control Register to “1”. A large percentage of the digital circuitry Analog SMSC 40 DATASHEET Datasheet Link Status bit in CAT-5 XFMR FARLOOPBACK bit of the Mode SMSC LAN8720A/LAN8720Ai ...

Page 41

... TXD 10/100 Ethernet RXD MAC Digital Ethernet Transceiver Figure 3.14 Connector Loopback Block Diagram SMSC LAN8720A/LAN8720Ai to “1”. In this mode, data that is received from the link partner on the MDI is TX XFMR RX Analog SMSC Figure 3.14. An RJ45 loopback cable can be used to route the transmit signals ...

Page 42

... RXER LED[2:1] 2 nRST Interface Figure 3.15 Simplified System Level Application Diagram Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720A/LAN8720Ai 10/100 PHY 24-QFN RMII TXP TXN RXP RXN XTAL1/CLKIN XTAL2 42 DATASHEET Datasheet Mag RJ45 25MHz SMSC LAN8720A/LAN8720Ai ...

Page 43

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 3.9.2 Power Supply Diagram (1.2V Supplied by Internal Regulator) 1uF VDDDIO Supply 1 Figure 3.16 Power Supply Diagram (1.2V Supplied by Internal Regulator) SMSC LAN8720A/LAN8720Ai LAN8720A/LAN8720Ai 24-QFN Ch.2 3.3V Core Logic Circuitry VDDCR Internal OUT IN Regulator Ch ...

Page 44

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720A/LAN8720Ai 24-QFN Ch.2 3.3V Core Logic Circuitry Internal VDDCR OUT IN Regulator (Disabled) VDDIO Ch.1 3.3V Circuitry C BYPASS LED1/ REGOFF ~270 Ohm 10k 44 DATASHEET Datasheet Power Supply 3.3V VDD2A C BYPASS VDD1A C BYPASS RBIAS 12.1k VSS SMSC LAN8720A/LAN8720Ai ...

Page 45

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 3.9.4 Twisted-Pair Interface Diagram (Single Power Supply) LAN8720A/LAN8720Ai Power 24-QFN Supply 3.3V VDD2A VDD1A TXP TXN RXP RXN Figure 3.18 Twisted-Pair Interface Diagram (Single Power Supply) SMSC LAN8720A/LAN8720Ai Ferrite bead 49.9 Ohm Resistors C BYPASS C Magnetics BYPASS C BYPASS 45 DATASHEET RJ45 1 2 ...

Page 46

... TXP TXN RXP RXN Figure 3.19 Twisted-Pair Interface Diagram (Dual Power Supplies) Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 49.9 Ohm Resistors C BYPASS C Magnetics BYPASS C BYPASS 46 DATASHEET Datasheet Power Supply 2.5V - 3.3V RJ45 1000 SMSC LAN8720A/LAN8720Ai ...

Page 47

... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN8720A/LAN8720Ai Table 4.1 Register Bit Types REGISTER BIT DESCRIPTION ...

Page 48

... PHY Special Control/Status Register Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 4.2 SMI Register Map REGISTER NAME 48 DATASHEET Datasheet GROUP Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8720A/LAN8720Ai ...

Page 49

... Note: Ignored if Auto-Negotiation is enabled (0.12 = 1). 7:0 RESERVED Note 4.1 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION Section 3.7.2, 31) is set from the register bit 49 DATASHEET ...

Page 50

... Extended Capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 50 DATASHEET Datasheet TYPE DEFAULT RO/ RO/LL 0b RO/ SMSC LAN8720A/LAN8720Ai ...

Page 51

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.2.3 PHY Identifier 1 Register Index (In Decimal): 2 BITS 15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION 51 DATASHEET TYPE DEFAULT R/W 0007h ...

Page 52

... Note 4.2 The default value of this field will vary dependant on the silicon revision number. Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 52 DATASHEET Datasheet TYPE DEFAULT R/W 110000b R/W 001111b R/W Note 4.2 SMSC LAN8720A/LAN8720Ai ...

Page 53

... Selector Field 00001 = IEEE 802.3 Note 4.3 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION 53 DATASHEET TYPE DEFAULT RO - R/W ...

Page 54

... Selector Field 00001 = IEEE 802.3 Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 54 DATASHEET Datasheet TYPE DEFAULT 00001b SMSC LAN8720A/LAN8720Ai ...

Page 55

... Page Received 0 = new page not yet received 1 = new page received 0 Link Partner Auto-Negotiation Able 0 = link partner does not have auto-negotiation ability 1 = link partner has auto-negotiation ability SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION 55 DATASHEET TYPE DEFAULT RO - ...

Page 56

... Refer to Power-Down," on page 38 0 RESERVED Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: DESCRIPTION for additional for additional Section 3.8.3.2, "Energy Detect for additional information. 56 DATASHEET Datasheet 16 bits TYPE DEFAULT R/W 0b SMSC LAN8720A/LAN8720Ai ...

Page 57

... Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 Note 4.5 The default value of this field is determined by the PHYAD[0] configuration strap. Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 31 information. SMSC LAN8720A/LAN8720Ai Size: DESCRIPTION Section 3.7.2, "MODE[2:0]: Mode for additional details. Section 3.7.1, for additional details ...

Page 58

... Note: This register is cleared on reset, but is not cleared by reading the register. This register does not increment in 10BASE-T mode. Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 58 DATASHEET Datasheet TYPE DEFAULT RO 0000h 16 ) and SMSC LAN8720A/LAN8720Ai ...

Page 59

... Enable Auto-MDIX 1 = Disable Auto-MDIX (use 27.13 to control channel) 14 RESERVED 13 CH_SELECT Manual channel select MDI (TX transmits, RX receives MDIX (TX receives, RX transmits) 12:11 RESERVED 10:5 RESERVED 4 XPOL Polarity state of the 10BASE- Normal polarity 1 = Reversed polarity 3:0 RESERVED SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION 59 DATASHEET TYPE DEFAULT R R ...

Page 60

... Parallel Detection Fault 1 INT1 0 = not source of interrupt 1 = Auto-Negotiation Page Received 0 RESERVED Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 60 DATASHEET Datasheet TYPE DEFAULT RO - RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/ SMSC LAN8720A/LAN8720Ai ...

Page 61

... BITS 15:8 RESERVED 7:1 Mask Bits 0 = interrupt source is masked 1 = interrupt source is enabled Note: Refer to Section 4.2.12, "Interrupt Source Flag Register," on page 60 for details on the corresponding interrupt definitions. 0 RESERVED SMSC LAN8720A/LAN8720Ai Size: 16 bits DESCRIPTION 61 DATASHEET TYPE DEFAULT RO - R/W 0000000b RO - Revision 1.2 (11-10-10) ...

Page 62

... Speed Indication HCDSPEED value: 001 = 10BASE-T half-duplex 101 = 10BASE-T full-duplex 010 = 100BASE-TX half-duplex 110 = 100BASE-TX full-duplex 1:0 RESERVED Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Size: 16 bits DESCRIPTION 62 DATASHEET Datasheet TYPE DEFAULT R/W 0000010b RO XXX RO - SMSC LAN8720A/LAN8720Ai ...

Page 63

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 5.2, "Operating applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified otherwise. SMSC LAN8720A/LAN8720Ai (Note 5. -0.5V to +3.6V (Note 5. -0.5V to +1.5V ...

Page 64

... DATASHEET Datasheet Note 5.4 for a Section VDDIO TOTAL TOTAL POWER CURRENT POWER PIN(mA) (mA) (mW) 0.6 49 159 0.5 45 148 0 Note 5 Note 5.6 0.2 7.4 25 0.2 6 5.8 16 Note 5.6 0.2 3.4 11.2 0.2 2.3 7 3.0 Note 5.6 SMSC LAN8720A/LAN8720Ai ...

Page 65

... Note: Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer. Note 5.7 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled. SMSC LAN8720A/LAN8720Ai VDDA3.3 VDDCR POWER POWER ...

Page 66

... I/O buffer characteristics. Typical values are MIN TYP MAX -0.3 3.6 1.01 1.19 1.39 1.39 1.59 1.79 336 399 459 - 0.4 VDD2A - 0.4 -0.3 0.35 1.4 VDD2A + 0.4 66 DATASHEET Datasheet UNITS NOTES Schmitt trigger V Schmitt trigger mV uA Note 5 12mA -12mA OH Note 5 SMSC LAN8720A/LAN8720Ai ...

Page 67

... Rise and Fall Symmetry Duty Cycle Distortion Overshoot and Undershoot Jitter Note 5.11 Measured at line side of transformer, line replaced by 100 Ω (+/- 1%) resistor. Note 5.12 Offset from 16nS pulse width at 50% of pulse peak. Note 5.13 Measured differentially. SMSC LAN8720A/LAN8720Ai 1.8V 2.5V 3.3V MIN TYP TYP TYP -0 ...

Page 68

... Figure 5.1 below. OUTPUT Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support SYMBOL MIN TYP V 2.2 OUT V 300 Figure 5.1 Output Equivalent Test Load 68 DATASHEET Datasheet MAX UNITS NOTES 2.5 2.8 V Note 5.14 420 585 mV SMSC LAN8720A/LAN8720Ai ...

Page 69

... Note: When the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and the 3.3V power supply. For additional information refer to "REGOFF: Internal +1.2V Regulator Configuration," on page SMSC LAN8720A/LAN8720Ai . Device power supplies can turn off in any order provided they all reach pon ...

Page 70

... MIN 25 0 100 200 1 2 for details. Configuration straps must only be pulled high or 70 DATASHEET Datasheet and t css csh for additional t csh t odad TYP MAX UNITS mS nS μ 800 nS (Note 5.15) Section 3.7, SMSC LAN8720A/LAN8720Ai ...

Page 71

... TXD[1:0], TXEN setup time to rising edge of su REFCLKO t TXD[1:0], TXEN input hold time after rising edge ihold of REFCLKO Note 5.16 Timing was designed for system load between 10 pf and 25 pf. SMSC LAN8720A/LAN8720Ai Section 3.7.4.2, "REF_CLK Out Mode," on page t clkp t t clkh clkl ...

Page 72

... MIN 20 t *0.35 clkp t *0.35 clkp 3.0 4.0 1.5 72 DATASHEET Datasheet t ohold t oval t ihold t su MAX UNITS NOTES ns t *0.65 ns clkp t *0.65 ns clkp 14.0 ns Note 5.17 ns Note 5.17 ns Note 5.17 ns Note 5.17 SMSC LAN8720A/LAN8720Ai ...

Page 73

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 5.5.4.3 RMII CLKIN Requirements Table 5.11 RMII CLKIN (REF_CLK) Timing Values PARAMETER CLKIN frequency CLKIN Frequency Drift CLKIN Duty Cycle CLKIN Jitter SMSC LAN8720A/LAN8720Ai MIN TYP MAX UNITS 50 MHz ± 50 ppm 40 ...

Page 74

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support for additional details. t clkp t t clkh clkl t ohold t Figure 5.6 SMI Timing Table 5.12 SMI Timing Values MIN 400 160 (80%) 160 (80 DATASHEET Datasheet Section 3.5, "Serial Management t su ihold MAX UNITS NOTES 300 SMSC LAN8720A/LAN8720Ai ...

Page 75

... The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. The total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 MHz. SMSC LAN8720A/LAN8720Ai Table 5.13 Crystal Specifications SYMBOL MIN ...

Page 76

... Terminal to Exposed Pad Clearance 76 DATASHEET Datasheet REMARKS Overall Package Height Standoff Mold Cap Thickness X/Y Body Size X/Y Mold Cap Size X/Y Exposed Pad Size Terminal Length Terminal Width Terminal Pitch SMSC LAN8720A/LAN8720Ai ...

Page 77

... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet SMSC LAN8720A/LAN8720Ai 77 DATASHEET Revision 1.2 (11-10-10) ...

Page 78

... Note: Standard reel size is 4000 pieces per reel. Revision 1.2 (11-10-10) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 78 DATASHEET Datasheet SMSC LAN8720A/LAN8720Ai ...

Page 79

... Rev. 1.0 (12-09-09) Document reworked for clarity and consistency with other SMSC documentation. Rev. 1.0 (04-15-09) Initial Release SMSC LAN8720A/LAN8720Ai Table 7.1 Customer Revision History Updated diagrams and tables to include RXER. Added timing note in Out Mode" Corrected signal names on RMII timing diagrams and tables ...

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