SI5023-BMR Silicon Laboratories Inc, SI5023-BMR Datasheet - Page 22

• Manufacturer Part Number: SI5023-BMR
• Description: Telecom Line Management ICs SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1
• Manufacturer: Silicon Laboratories Inc
• Type: Evaluation Board For Si5023 Siphy Multi-Rate Sonet/ Sth Clock and Data Recovery ICr

Specifications of SI5023-BMR

• Mounting Style: SMD/SMT
• Package / Case: MLP-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5023
5. Pin Descriptions: Si5023
22
Pin #
1,2
3
4
RATESEL0,
SLICE_LVL
RATESEL1
Pin Name
LOS_LVL
Figure 21. Si5023 Pin Configuration
I/O
Table 9. Si5023 Pin Descriptions
I
I
I
SLICE_LVL
RATESEL0
RATESEL1
REFCLK+
LOS_LVL
REFCLK-
LOL
Signal Level
1
2
3
4
5
6
7
28
LVTTL
8
27
9
Top View
Rev. 1.3
26
10
GND
Pad
25
11
24
12
23
13
Data Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Notes:
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 14 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
22
14
1. These inputs have weak internal pullups.
2. After any change in RATESEL, the device must be
21
20
19
18
17
16
15
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT-
GND
reset.
Description