LX128C-32FN208C Lattice, LX128C-32FN208C Datasheet - Page 48

• Manufacturer Part Number: LX128C-32FN208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 1.8V, SERDES, 3.2ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128C-32FN208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysCLOCK PLL Timing
t
t
t
t
f
f
f
f
f
f
t
t
T
t
t
t
t
t
t
1. This condition assures that the output phase jitter will remain within specification. Jitter specification is based on optimized M, N and V set-
2. Accumulated jitter measured over 10,000 waveform samples
PWH
PWL
R
INSTB
MDIVIN
MDIVOUT
NDIVIN
NDIVOUT
VDIVIN
VDIVOUT
OUTDUTY
JIT(CC)
CLK_OUT_DLY
PHASE
LOCK
PLL_DELAY
RANGE
PLL_RSTW
JIT(PERIOD)
, t
tings determined by the ispLEVER software.
Symbol
F
2
Input clock, high time
Input clock, low time
Input Clock, rise and fall time
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
Output clock, duty cycle
Output clock, cycle to cycle jitter (peak)
Output clock, period jitter (peak)
Input clock to CLK_OUT delay
Input clock to external feedback delta
Time to acquire phase lock after input stable
Delay increment (Lead/Lag)
Total output delay range (lead/lag)
Minimum reset pulse width
Parameter
Over Recommended Operating Conditions
45
80% to 80%
20% to 20%
20% to 80%
Clean reference
10 MHz ≤ f
100 MHz ≤ f
Clean reference
40 MHz ≤ f
160 MHz ≤ f
Clean reference
10 MHz ≤ f
100 MHz ≤ f
Clean reference
40 MHz ≤ f
160 MHz ≤ f
Internal feedback
External feedback
Typical = +/- 250ps
MDIVOUT
MDIVOUT
MDIVOUT
MDIVOUT
VDIVIN
VDIVIN
VDIVIN
VDIVIN
Conditions
1
1
1
1
:
:
:
:
≤ 160 MHz
≤ 400 MHz
≤ 160 MHz
≤ 400 MHz
≤ 40 MHz or
≤ 320 MHz and
≤ 40 MHz or
≤ 320 MHz and
ispGDX2 Family Data Sheet
+/- 0.84 +/- 3.85
+/- 120 +/- 550
Min
100
0.5
0.5
1.8
10
10
10
10
10
40
—
—
—
—
—
—
—
—
—
+/- 300
+/- 600
+/- 150
+/- 600
+/- 150
Max
320
320
320
320
400
320
500
3.0
3.4
60
—
—
25
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ps
ps
ps
ps
ps
ns
ps
us
ps
ns
ns
%