ISPGDX120A-5Q160 Lattice, ISPGDX120A-5Q160 Datasheet - Page 15

• Manufacturer Part Number: ISPGDX120A-5Q160
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX120A-5Q160

• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 120 x 120
• Package / Case: TSSOP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. NC pins are not to be connected to any active signals, VCC or GND.
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Descriptions
Signal Locations: ispGDX160A
I/O
TOE
RESET
Y0, Y1, Y2, Y3
BSCAN/ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TDO/SDO
GND
VCC
NC
TOE
RESET
Y0, Y1, Y2, Y3, 75, 76, 180, 181
BSCAN/ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TDO/SDO
GND
VCC
NC
Signal Name
1
1
Signal
178
185
183
81
80
79
78
6, 15, 25, 35, 44, 54, 63, 77, 91, 100, 110, 119, 129, A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12,
139, 148, 159, 168, 182, 195, 204
1, 17, 33, 49, 65, 89, 105, 121, 137, 153, 170, 184
193
73, 74, 156, 179
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each
may be independently latched, registered or tristated. They can also each assume one other control
function (OE, CLK and MUXsel as described in the text).
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
Active LOW Input Pin – Resets all I/O register outputs when LOW.
Input Pins – Dedicated clock input pins. Each pin can drive any or all I/O cell registers.
Input Pin – When HIGH, this pin enables the Boundary Scan Test and Programming Interface. When
LOW, this pin enables the Lattice ISP protocol for programming and tristates all I/O pins, except those
used for the programming interface.
Input/Input Pin – Serial data input during ISP programming or Boundary Scan mode.
Input/Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
Input/Input Pin – Control input during ISP programming or Boundary Scan mode.
Output/Output Pin – Serial data output during ISP programming or Boundary Scan mode.
Ground (GND)
Vcc – Supply voltage (5V).
No Connect.
208-Pin PQFP
14
Description
Specifications ispGDX Family
A12
D10
V10, Y10, C11, A11
B10
Y12
U11
V11
W11
K9, K10, K11, K12, L9, L10, L11, L12, M9, M10,
M11, M12, N4, N17, U4, U8, U13, U17
D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10,
U15
A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11,
B14, B18, B19, B20, C2, C3, C10, C18, D2, D3, D16,
E2, E17, E19, H1, H3, H18, H20, K20, L1, N1, N3,
N18, N20, T2, T4, T19, U5, U18, U19, V3, V14, V18,
V19, W1, W2, W3, W7, W10, W14, W19, W20, Y1,
Y2, Y6, Y9, Y11, Y18, Y20
272-Ball BGA