LAN9115-MD SMSC, LAN9115-MD Datasheet - Page 81

• Manufacturer Part Number: LAN9115-MD
• Description: Ethernet ICs Efficient Sngl Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
5.3.9
31-21
16-19
BITS
15-7
6-5
20
4
DESCRIPTION
Reserved
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See
Configurable FIFO Memory Allocation," on page 82
Reserved
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
Notes:
Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note:
This field does not control multiplexing of the SMI port or other MII signals.
There are restrictions on the use of this field. Please refer to
"MII Interface - External MII Switching," on page 44
HW_CFG—Hardware Configuration Register
This register controls the hardware configuration of the LAN9115 Ethernet Controller.
Note: The transmitter and receiver must be stopped before writing to this register. Refer to
---------------------------------------------------
[6]
0
0
1
1
Offset:
This bit does not control the multiplexing of other MII signals.
[5]
3.13.8, "Stopping and Starting the Transmitter," on page 56
Starting the Receiver," on page 60
0
1
1
0
MII Clock Source
Internal PHY
External MII Port
Clocks Disabled
Internal PHY
74h
Section 5.3.9.1, "Allowable settings for
DATASHEET
81
for details on stopping the transmitter and receiver.
for more information.
Size:
for details.
Section 3.12,
and
32 bits
Section 3.14.4, "Stopping and
TYPE
R/W
R/W
R/W
R/W
RO
RO
Revision 1.5 (07-11-08)
DEFAULT
00b
5h
0
0
-
-
Section