LAN91C96IQFP SMSC, LAN91C96IQFP Datasheet - Page 125
![Ethernet ICs Non-PCI 10 Mbps Ethernet MAC](/photos/27/13/271359/lan9116_sml.jpg)
LAN91C96IQFP
Manufacturer Part Number
LAN91C96IQFP
Description
Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN91C96-MU.pdf
(125 pages)
Specifications of LAN91C96IQFP
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
95 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Chapter 13 LAN91C96 Revisions
SMSC LAN91C96 5v&3v
PAGE(S)
124~125
108
108
92
65
50
17
58
61
59
67
70
38
38
25
80
38
38
25
80
56
21
92
99
~
2
2
1
Ordering Information
All
Ordering Information
DC Electrical Characteristics
Theory of Operation (Magic Packet
Support section)
I/O Space – Bank1 Offset 2
Fig.12.28100 pin QFP Package;
Fig.12.28100 Pin TQFP Package;
Chapter 4 Description of Pin
Functions
IO Space Bank 2 Offset 2 – Interrupt
Figure 7.1 – Interrupt Structure
Bank 3 Offset A – Revision Register
8.1, 8.2 Typical Flow of Events for
Transmit
Title and document
Figure 8.1 – Interrupt Service Routine
Figure 6.1 – Data Frame Format
Data area in ram
Figure 7
DC Electrical Characteristics
Figure 15
Figure 6.1 – Data Frame Format
Data area in ram
Figure 7
DC Electrical Characteristics
Figure 15
I/O Space – Bank 2/ Top of RX FIFO
Packet Number
Buffer Symbols
DC Electrical Characteristics
Timing Diagrams
SECTION/FIGURE/ENTRY
DATASHEET
Page 125
Leaded removed
Fixed various typos
Added lead-free ordering information
Modified Supply Current in power down
mode
Modified descriptions of Magic Packet
Support
Modified I/O base address 300h
decoding
Updated Pin Package diagrams
Added description of RBIAS pin
Modified the description of Interrupt
Registers
Modified Interrupt Structure Figure
Changed the REV ID to 9
Modified the flow chart
Non-PCI replaced ISA/PCMCIA in title.
Local Bus replaced ISA throughout
document.
Figure has been updated.
Max Offset changed to 1534 from 1536
Number of Bytes in Data Area changed
to 1531 from 2034
Updated Figure 7
Updated 3.3V Characteristic Numbers
replaced TBD
Updated figure 15
Max Offset changed to 1534 from 1536
Number of Bytes in Data Area changed
to 1531 from 2034
Updated Figure 7
Updated 3.3V Characteristic Numbers
replaced TBD
Updated figure 15
MMU Commands changed from 3, 4 to
6, 8
See italicized text
See italicized text
Updated table - see italicized text
Figures: 20-23, 25, 29, 31-33, 35-37
CORRECTION
Revision 1.0 (10-24-08)
10/24/08
07/28/08
09/10/04
08/11/04
08/11/04
09/30/02
09/17/02
07/01/02
07/01/02
07/01/02
07/01/02
07/01/02
04/15/02
04/15/02
07/27/01
07/27/01
07/27/01
07/27/01
03/21/01
07/27/01
07/27/01
07/27/01
07/27/01
03/21/01
07/18/00
06/29/00
06/29/00
06/29/00
REVISED
DATE
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