LAN91C96IQFP SMSC, LAN91C96IQFP Datasheet - Page 35
![Ethernet ICs Non-PCI 10 Mbps Ethernet MAC](/photos/27/13/271359/lan9116_sml.jpg)
LAN91C96IQFP
Manufacturer Part Number
LAN91C96IQFP
Description
Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN91C96-MU.pdf
(125 pages)
Specifications of LAN91C96IQFP
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
95 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7S
8S
4
5
6
7
8
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
By writing a 0 to
CTR PWRDWN and
0 to WAKEUP_EN
bits
By writing 1 to
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN
By writing 1 to
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN, and 0 to
WAKEUP_EN bit
By writing 0 to
ECSR Power Down
bit*
By writing 0 to
ECSR Power Down
and a 0 to CTR
PWRDWN bit
By writing 0 to
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
By writing 0 to
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
WAKES UP BY
PCMCIA Attribute Memory
Address 0- 7FFEh
The Attribute Memory is implemented using an external parallel EEPROM, ROM or Flash ROM. A parallel
EEPROM (or equivalent external device) must be used for CIS.
In LOCAL BUS mode, serial EEPROM is used for configuration and IEEE Node address making it software
compatible to the LAN9xxx family of Ethernet LAN Controllers. The EEPROM is optional for both LOCAL BUS
and PCMCIA requiring a Minimum size of 64 X 16 bit word addresses.
The LAN91C96 generates the appropriate control lines (nFCS and nFWE) to read and write the Attribute
memory, and it tri-states the data bus during external Attribute Memory accesses. Only even locations are
used.
PWR DWN PIN
(A= ASSRTD)
nA
nA
nA
nA
nA
nA
nA
DATASHEET
ENABLE
ECOR
FUNC
1
1
1
1
1
1
1
Page 35
NEXT STATE
DOWN
ECSR
PWR
0
0
0
0
0
0
0
PWRDWN
CTR
BIT
0
0
0
0
0
0
0
WAKEUP_EN
CTR
BIT
0
0
0
0
0
0
0
Revision 1.0 (10-24-08)
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
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