STD90N03L STMicroelectronics, STD90N03L Datasheet - Page 9

• Manufacturer Part Number: STD90N03L
• Description: MOSFET N-CH 30V 80A DPAK
• Manufacturer: STMicroelectronics
• Series: STripFET™r

Specifications of STD90N03L

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 5.7 mOhm @ 40A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 80A
• Vgs(th) (max) @ Id: 1V @ 250µA
• Gate Charge (qg) @ Vgs: 32nC @ 5V
• Input Capacitance (ciss) @ Vds: 2805pF @ 25V
• Power - Max: 95W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.0057 Ohm @ 10 V
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 80 A
• Power Dissipation: 95000 mW
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-7979-2; STD90N03L

STD90N03L - STD90N03L-1
Appendix A
Figure 16. Buck Converter: Power Losses Estimation
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
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The high side (SW1) device requires:
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Very low R
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon;
Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the
gate
Small Qg to have a faster commutation and to reduce gate charge losses
Low R
DS(on)
DS(on)
to reduce the conduction losses.
to reduce conduction losses
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