STV5730A STMicroelectronics, STV5730A Datasheet - Page 2
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STV5730A
Manufacturer Part Number
STV5730A
Description
Multimedia Misc On-Screen Display
Manufacturer
STMicroelectronics
Type
Satellite Receiverr
Datasheet
1.STV5730A.pdf
(20 pages)
Specifications of STV5730A
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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PIN DESCRIPTION
STV5730A
2/20
N
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
o
VIDEO OUT2 Analog Output If the M7 mode bit is cleared : this pin is a CVBS output that delivers the
VIDEO OUT1 Analog Output This is a CVBS output. It delivers the VIDEO IN + text in mixed mode and the
LESCREEN
XTAL OUT
VIDEO IN
LECHAR
XTAL IN
CSYNC
DGND
YOUT
MUTE
AGND
COUT
Name
DATA
DV
AV
CSN
RES
FTR
BAR
CLK
CIN
YIN
CO
FB
G
R
B
DD
DD
Analog Output This pin outputs the luma to allow the user to notch filter it. This pin may be
Analog Output This pin outputs the full page mode chroma for external filtering (and
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Bidirectional
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Analog Pin
Analog Pin
Supply Pin
Supply Pin
Supply Pin
Supply Pin
Type
Pin
connected to the YIN input for minimum cost applications.
This is the CVBS input. An external capacitor is needed for clamp operation.
The STV5730A extracts the sync from this signal when the C7 control bit is
set.
it must be tied to an external resistor to control the PLL f0 frequency.
it must be tied to the line PLL loop filter.
5V analog supply pin.
5V digital supply pin.
This pin inputs the mixed mode composite sync when the C7 control bit is
cleared. It outputs the video in extracted sync when the C7 control bit is set.
This is the 4*fsc quartz input. The quartz may be started or stopped under
control of dedicated serial interface messages. Alternatively, a 4fsc clock can
be input directly. The stop message must not be used in this case.
This is the 4*fsc quartz output. The quartz may be started or stopped under
control of dedicated serial interface messages.
This pin indicates if the CVBS input signal is present on VIDEO IN input pin.
It is forced low if the M2 mode bit is cleared.
This is the serial interface data input.
This is the serial interface clock input.
This is the serial interface chip select input.
This is the Red signal output. It is forced low during the horizontal and vertical
blanking intervals.
This is the Green signal output. It is forced low during the horizontal and
vertical blanking intervals.
This is the Blue signal output. It is forced low during the horizontal and vertical
blanking intervals.
This is the fast blanking output. It is delivered to control an external R/G/B
switch for R/G/B or TV applications.
This is the character activity output. It indicates if a character foreground is
being displayed, and can be used to control its intensity.
This input forces the PLL in free run mode when active. It is enabled if the M0
mode bit is set.
0V digital ground.
0V analog ground.
This pin determines the character intensity level in external bias mode (ie
when the C10 control bit is set). This level must be defined relative to the
internal black reference. A variable luminance signal may be entered. To be
grounded if not used.
This pin determines the screen intensity level in external bias mode (ie when
the C10 control bit is set). This level must be defined relative to the internal
black reference. A variable luminance signal may be entered. To be grounded
if not used.
attenuation if necessary). This pin may be connected to CIN for minimum cost
applications.
This pin inputs the filtered chroma.
VIDEO IN signal. The sync is re-inserted if the M4 mode bit is set. The output
amplitude may be either 0dB or +6dB according to the M5 mode bit.
If the M7 mode bit is set : It outputs the currently active synchronism. The
signal amplitude is controlled by the M5 mode bit.
If the M8 mode bit is cleared : VIDEO OUT2 is in high impedance state.
CVBS text in full page mode. The output signal amplitude may be either 0dB
or 6dB according to the M5 mode bit. The sync is re inserted if the M4 mode
bit is set.
This pin inputs the notch filtered luma.
Description