STV2310D STMicroelectronics, STV2310D Datasheet
STV2310D
Specifications of STV2310D
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STV2310D Summary of contents
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... TV processor STV3500, STV3600 for digitized 100-Hz/ ProScan CRT TVs companion chip to the TV processor STV3550 for LCD-TVs. STV2310 TQFP64 14x14x1.4 mm (Thin Quad Flat Package) ORDER CODE: STV2310D/DT TQFP64 10x10x1.4 mm (Thin Quad Flat Package) ORDER CODE: STV2310SD/SDT 1/113 ...
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Figure 1: STV2310 Block Diagram STV2310 ...
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STV2310 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description ............................................................................................................................. 29 4.11.2 Programming ....................................................................................................................................... 29 4.12 Output FIFO and Line-locked Ouput Pixel Clock Generator ..............................................29 4.12.1 General Description ............................................................................................................................. 29 4.12.2 Output Data ......................................................................................................................................... 30 4.12.3 Insertion of Ancillary Data .................................................................................................................... 40 4.12.4 Line-Locked Output Pixel ...
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STV2310 Chapter 7 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description 1 General Description The STV2310 is a high-quality video front-end circuit for processing all analog standards into a digitalized 4:2:2 YCrCb video format. It processes NTSC/PAL/SECAM CVBS signals, as well as conventional analog RGB or YCrCb signals. This ...
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STV2310 either by an embedded crystal oscillator or an external clock generator (27 MHz).The only exception is the output stage which operates at the line-locked output pixel clock frequency. CVBS1/Y CVBS2/Y C Analog Input Stage R/Cr G B/Cb FB SDA ...
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General Description 1.8 V ANA 1 64 CVBS1/Y 63 CVBS2 3.3 V ANA 56 ADC SHIELD 47 R_CR 51 G ADC 52 53 B_CB 48 Optional 1.8 V ANA 50 54 1.8 ...
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STV2310 2 Pin Allocation and Description 2.1 Pinout Diagram CC18_CVBS VBS2_Y DD18_CORE S T_MODE DD18_CORE DD18_CORE S RESET DD33_IO S_IO CADD 2.2 Pin Descriptions Pin Pin Name Analog 1 VCC18_CVBS GND_SUB 38 VCC18_SUB 39 ...
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Pin Allocation and Description Pin Pin Name 40 GND_CLK 45 SHIELD 49 VCC18_RGB 50 GND_RGB 54 VCC18_DIG 55 GND_DIG 56 GND_IO 57 VCC33_IO 64 GND_CVBS Digital 4 VDD18_CORE 5 VSS 7 VDD18_CORE 8 VSS 11 VDD18_CORE 12 VSS 14 VDD33_IO ...
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STV2310 Pin Pin Name 58 ADCIN 59 VIDEOCOMM 60 VIDEO_OUT 61 REFP_CVBS 62 REFM_CVBS 63 CVBS1_Y Pin Pin Name 19 YCRCB7 20 YCRCB6 21 YCRCB5 22 YCRCB4 25 YCRCB3 26 YCRCB2 27 YCRCB1 28 YCRCB0 31 CLK_DATA 32 PLLLOCK/IRQ 33 ...
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Pin Allocation and Description Pin Pin Name 6 TST_MODE 9 SDA 10 SCL 13 NRESET 16 I2CADD 12/113 Table 5: Configuration Pins Type Connected to Ground I/O I²C Bus Data I/O I²C Bus Clock I Active Low ...
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STV2310 3 Default Setup At Reset The default configuration at reset is: CVBS1_ input active ● Fast Blanking input for RGB insertion enable ● Automatic Standard Recognition of NTSC/PAL/SECAM ● Comb filter enable ● Data slicer enable ● Output ITU_R ...
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Functional Description 4 Functional Description 4.1 Analog Input Stage 4.1.1 General Description The Analog Input Stage provides the interface between the incoming video signals and the Analog- to-Digital Converters (ADC) using Clamp and Automatic Gain Control (AGC) stages to fit ...
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STV2310 magnitude by ± logarithmic steps to the optimal range of the A/D Converter. The video signal then goes through an external anti-aliasing filter before reaching the A/D Converter. The A/D Converter dedicated to the CVBS/Y channel ...
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Functional Description Analog R_PR, G and B_PB signals are clamped to the black level during the back porch period. These signals are digitized by a triple 8-bit A/D converter recommended that an external anti- aliasing filter be added ...
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STV2310 The Output Sync Pulse (H, V and F) can be embedded in the digital output stream, according to the ITU_R BT_656/601 format, using the EAV and SAV codes. The Output Sync Pulse can also be delivered on dedicated external ...
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Functional Description The external HSync pulse can be synchronised to the End of Active Video (EAV) and the Start of Active Video (SAV) pulses, or initialized according to the usual analog H/V pulse using the HSYNC_SAV bit in the CVBS ...
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STV2310 The practical value of the 4.4 Luminance and Chrominance Separation 4.4.1 General Description The Y/C Separator separates the chrominance (C) component from the composite signal which also includes the luminance (Y), synchronization and color burst (subcarrier) ...
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Functional Description The notch filter width used in the Y/C separation can be adjusted from narrow to wide by the BW_SEL[2:0] bits in the DEM_YC_DELAY[3:0] bits in the 20/113 DDECCONT18 register. Luma Chroma delay can be adjusted by the DDECCONT15 ...
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STV2310 4.5 Standard Research Sequence Programming The chroma signal is sent to the Standard Identifier and Chroma Demodulator. The Standard Identifier performs an automatic recognition sequence for one of the following standards. Chroma Standard PAL B,D,G,H,I SECAM NTSC M PAL ...
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Functional Description Note 1: Codes 110 and 111 are associated with “No Standard”. From this list of possible standards, the user must complete the Automatic Standard Recognition table required for the automatic search. Identification will be restricted to the table ...
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STV2310 After the confirmation step has been successful, the standard is considered as identified. The TVSTID flag is set in the TVSTD[2:0] bits of the 4.6 Standard Identification The input signal standard is automatically recognized using a proprietary ST patented ...
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Functional Description Figure 13: Phase Correction when Automatic Flesh Control Enabled Phase Correction (cϕ) +10 ϕ - 39.4° 0 -10 4.8 Soft Mixer 4.8.1 General Description The Soft Mixer is used to mix the Y, Cr and Cb data flows ...
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STV2310 When one of the Alpha Blending modes is used for mixing, the alpha value is set in the MIX_SLOPE[7:0] bits. When the STV2310 is in normal RGB and CVBS mixing mode, the MIX_SLOPE[3:0] bits indicate the mixing slope (duration ...
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Functional Description The output formatting can be performed with Normal or Square Pixel modes. For Square Pixel mode, the number of required samples per line depends on the input standard. Table 11: Required Samples per Line for Square Pixel Mode ...
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STV2310 4.9.1.4 Panorama Mode (Non-Linear Scaling) To better display wider TV screen aspect ratios, Panorama mode applies a different zoom factor to the center of the image in relation to the edges; i.e. a Non-Linear Scaling mode must be implemented. ...
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Functional Description The ZOOMIN_FACT bits determine the zoom-in factor at the left and right edges of the picture ● The ZOOMOUT_FACT bits determine the zoom-out factor at the center of the picture ● The ZOOMIN_OFFSET bits determine the border width ...
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STV2310 4.10.2 Programming To enable the CrCb overload mechanism, set the CRCBOVER_EN bit in the The automatic gain for the RGB is set in the 4.11 Analog YCrCb Mode 4.11.1 General Description The STV2310 can be programmed in Analog YCrCb ...
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Functional Description 4.12.2 Output Data There are 4 data output standards which are a combination of 525/625 input standards and Normal/ Square pixel format. There are four possible multiples: 1716 or 1728 in Normal Pixel mode, ● 1560 or 1888 ...
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STV2310 4.12.2.1 Vsync Output Pin Modes 525 Line / 60 Hz Modes Field (F) Output Standard 1 1716 bytes line 3 line 4 Blanking Field Odd Field 1 Active Video line 265 line 266 Blanking Field ...
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Functional Description For all output standards, the Vsync output signal changes twice per frame. The Vsync signal (pin 34) can be generated at the output in one of two modes: 1 “Digital“ Vsync mode: The VSYNC signal always changes at ...
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STV2310 4.12.2.4 Output Standard 1 : Normal Pixel mode / 525 lines / 60 Hz (NTSC) EAV code description of EAV code on 4 bytes SAV code ...
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Functional Description 1716 bytes line 4 Blanking Field 1 (F=0) Field 1 Odd Active Video line 266 Blanking Field 2 Field 2 (F=1) Active Video Even line 3 H=0 SAV H=1 EAV Note that the vertical blanking interval has been ...
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STV2310 4.12.2.5 Output Standard 2: Normal Pixel / 625 lines / 50 Hz (PAL & SECAM) EAV code description of EAV code on 4 bytes SAV code ...
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Functional Description 1728 bytes line 1 Blanking Field 1 (F=0) Field 1 Odd Active Video line 313 Blanking Field 2 Field 2 (F=1) Active Video Even line 625 Blanking H=0 SAV H=1 EAV Note that the vertical blanking interval has ...
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STV2310 4.12.2.6 Output Standard 3: square pixel / 625 lines / 50Hz (PAL SECAM) EAV code description of EAV code on 4 bytes SAV code description of ...
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Functional Description 1888 bytes line 1 Blanking Field 1 (F=0) Field 1 Odd Active Video line 313 Blanking Field 2 Field 2 (F=1) Active Video Even line 625 Blanking H=0 SAV H=1 EAV Note that the vertical blanking interval has ...
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STV2310 4.12.2.7 Output Standard 4: Square Pixel / 525 lines / 60Hz (NTSC) EAV code description of EAV code on 4 bytes SAV code description of SAV ...
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Functional Description 1560 bytes line 4 Blanking Field 1 (F=0) Field 1 Odd Active Video line 266 Blanking Field 2 Field 2 (F=1) Active Video Even line 3 H=0 SAV H=1 EAV Note that the vertical blanking interval has been ...
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STV2310 The ancillary data is always inserted between the EAV and SAV codes of each line. The line number is provided by the VBI slicer.VBI data is inserted on the next possible output line. The only lines where insertion cannot ...
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Functional Description To force the pass through mode, use the PASSTHROUGH_EN bit in the To shift the external Hsync pulse, use the HSYNCSHIFT_DEL[1:0] and HSYNCSHIFT_EN bits in the DDECCONT22 register attenuation are controlled by the DDECCONT37 and the ...
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STV2310 Note: The WST - Teletext C and D (525 lines /60 Hz) formats (NATBS - MOJI) may be covered by the WST - Teletext B (525 lines -60 Hz) format. 4.13.1 VBI Formatting Features 4.13.1.1 VPS Features Video Programming ...
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Functional Description Generation of Per-byte Parity check flags. ● 4.13.1.5 Gemstar Features Search of Gemstar data during the line 21 (NTSC) or line 22 (PAL), regardless of the field ● information. Optional Extended slicing during all the VBI (line 5 ...
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STV2310 Ancillary Data Flow For each TV line, the following sequence is generated immediately after the EAV code: ADF 3 Bytes 1 Byte 00h - FFh - FFh 41h DID & SDID Coding Convention All VBI data formats recognized by ...
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Functional Description Data Count (DC) Coding The Data Count (DC) byte is coded according to the parity protection scheme defined in SMPTE 291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data (i.e. bit 6 is the even parity ...
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STV2310 Bit 7 Page Byte Bit 6 Even parity Coding 1’s complement check for bits [5:0] In both cases, two filler bytes are added immediately after the last meaningful User Data Word in order to maintain a Data Count value ...
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Functional Description UDW Coding for VPS In Video Programming Systems (VPS), a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits Bit 7 is the complement of bit 6. ...
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STV2310 VPUD31: This byte provides the MSB contents of VPS byte 13. ● bit 7 6 ASM[5:0]Announced start minute. NC[3:0]Nationality code which is used to identify the source of the item. VPUD40: This byte provides the LSB contents of VPS ...
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Functional Description WSUD01: This byte provides the MSB contents of the WSS 1st group of data. ● bit 7 WSSER1:WSS data group 1 error flag. This bit is set when any of the Group 1 bits (WSS[3:0]) is received with ...
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STV2310 UDW Coding for CC In Closed Caption (CC) systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits Bit 7 is the complement of bit 6. ADF ...
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Functional Description UDW Coding for Gemstar In US Gemstar systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits Bit 7 is the complement of bit 6. ADF ...
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STV2310 GMUD31: This byte provides the MSB contents of the Gemstar 4th byte of data. ● bit GMUDL0: This byte provides the contents of the Gemstar bytes parity check. ● bit GMUDL1: This byte is static and provide no information. ...
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Functional Description I2CADD = 0 Write Address Read Address For the exact numerical values of the I²C timing characteristics, please refer to the Characteristics on page 54/113 Table 23: Alternate I²C Addresses I2CADD = 1 86h Write Address 87h Read ...
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STV2310 5 Register List This section lists the Control and Status registers for the I²C interface. Registers are called as output ports and are named as follows: DDECCONT[n][7:0] for non-VBI Control registers ● DDECSTAT[n][7:0] for Status registers (Read Only) ● ...
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Register List Add. Reset Value Name (h) (Bin) DDECCONT1 13h 0000 0000 3 DDECCONT1 14h 0000 0000 4 DDECCONT1 15h 0001 0000 5 DDECCONT1 16h 0111 1010 6 DDECCONT1 17h 0110 0100 7 DDECCONT1 18h 0101 1001 8 DDECCONT1 19h ...
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STV2310 Add. Reset Value Name (h) (Bin) DDECCONT2 26h 0100 0100 6 DDECCONT2 27h 0110 0110 7 DDECCONT2 28h 1000 0010 8 DDECCONT2 29h 0101 0101 9 DDECCONT2 2Ah 1000 0010 A DDECCONT2 2Bh 0110 0011 B DDECCONT2 2Ch 1000 ...
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Register List Add. Reset Value Name (h) (Bin) DDECCONT3 39h 0101 0101 9 DDECCONT3 3Ah 0101 0101 A DDECCONT3 3Bh 0011 0101 B DDECCONT3 3Ch 1111 1100 C VBICONT1 3Dh xx00 0001 VBICONT2 3Eh xx00 0000 VBICONT3 3Fh 1000 0001 ...
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STV2310 Add. Reset Value Name (h) (Bin) DDECCONTF 7Eh 0000 0000 E DDECCONTF 7Fh 0000 0000 F DDECSTAT1 80h 0001 0000 DDECSTAT2 81h READ ONLY DDECSTAT3 82h READ ONLY DDECSTAT4 83h READ ONLY DDECSTAT5 84h READ ONLY DDECSTAT6 85h READ ...
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Register List Bit Name PIXMODE Pixel Mode Selection In Square Pixel mode, the number and Cb components depends on the standard as shown in Table 12 . The output line locked frequency (CLK_DATA) will also change according ...
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STV2310 Bit Name BLANKMODE Blanking Mode [1:0] The blanking mode defines how the clamp mechanism will perform. The blanking code is the ADC output code used by the clamp mechanism as target In the Auto mode and depends on the ...
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Register List DDECCONT3 Address (hex): 03h Reset Value (bin): 0001 0111 Bit 7 Bit 6 Bit Name Bits[7:6] Reserved: Must be set to 0. AUTOSTD[17:12] Auto Identification Table (Third and Fourth Standards) Third and Fourth Standards of the Automatic Standard ...
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STV2310 Bit Name CRCBOVER_EN RGB enables the CRCB overload algorithm This bit enables the RGB CrCb overload mechanism. This mechanism is used to prevent clipping on YCrCb (when the input RGB signals are too large). The CrCb overload mechanism performs ...
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Register List Bit Name MIX_SLOPE[7:0] Soft Mixing Slope, Alpha Blending or Saturated Value This bitfield provides the soft mixing slope or the alpha blending value depending on Fast Blanking mode. When the blanking mode is in Forced RGB or Forced ...
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STV2310 DDECCONT9 Address (hex): 09h Reset Value (bin): 0100 0000 Bit 7 Bit 6 Bit Name ZOOMOUT_ Zoom-out Factor from 1 to 0.25 (MSBs) FACT [9:2] The Zoom-out factor operates from 1 (no zoom) to 0.25 (large zoom). The Zoom-out ...
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Register List Bit Name ZOOMOUT_FAC Zoom-out Factor (LSBs). See register T [1:0] ZOOMIN_OFFSE Zoom-in Offset (LSBs). See register T[1:0] ZOOMOUT_EN Zoom-out Function Enable When both Zoom-in and Zoom-out functions are enabled, the STV2310 is in Panorama mode. In Panorama mode, ...
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STV2310 DDECCONTD Address (hex): 0Dh Reset Value (bin): 0011 0100 Bit 7 Bit 6 STI_NB_FIELDS_FALSE [1:0] Bit Name Bit 7 Reserved: Must be set to 0. STI_NB_FIELDS Number of Fields where Identification is lost before declaring Loss of Identification _FALSE[1:0] ...
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Register List Bit Name Bits [5:0] Reserved. Must be set to 0. Bit 6 Reserved. Must be set to 0. Bit 7 Reserved. Must be set to 0. DDECCONTF Address (hex): 0Fh Reset Value (bin): 0000 0000 Bit 7 Bit ...
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STV2310 DDECCONT11 Address (hex): 11h Reset Value (bin): 1000 1000 Bit 7 Bit 6 SYNC_SLICE_LEVEL[3:0] Bit Name SYNC_SLICE_LE Slicing Level Value VEL[3:0] The horizontal PLL requires a slicing level . This bitfield indicates the slicing level as a fraction between ...
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Register List DDECCONT13 Address (hex): 13h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit Name Bits[7:0) Reserved: Must be set to 0000 0000. DDECCONT14 Address (hex): 14h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit Name ...
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STV2310 DDECCONT16 Address (hex): 16h Reset Value (bin): 0111 1010 Bit 7 Bit 6 SATLMTLN[1:0] Bit Name SATLMTLN[1:0] AGC Saturation Limit (Points/Lines) SATLMTPT[1:0] The SATLMTPT[1:0] and SATLMTLN[1:0] bits are used to program the CVBS Saturation Threshold expressed as ...
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Register List Bit Name STI_NB_FIELDS Number of Fields to be Confirmed _CONFIRM[2:0] This bitfield operates on the second stage of the standard identification algorithm: the confirmation stage. It gives the number of consecutive fields where the standard criteria must be ...
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STV2310 Bit Name NONINTERLACE Analog Output as Input Bit D_EN This bit enables the "analog output as input" mode only operational when the o_vsynctype is set to the analog mode (see register o_ddeccont0[7] bit) When the o_vsynctype is ...
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Register List DDECCONT1B Address (hex): 1Bh Reset Value (bin): 1000 0100 Bit 7 Bit 6 Bit Name Bits[7:4] Reserved: Must be set to 1000 Bits[3:0] Reserved: Must be set to 0100 DDECCONT1C Address (hex): 1Ch Reset Value (bin): 1000 0100 ...
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STV2310 DDECCONT1E Address (hex): 1Eh Reset Value (bin): 1001 1001 Bit 7 Bit 6 Bit Name Bits[7:4] Reserved: Must be set to 1001 Bits[3:0] Reserved: Must be set to 1001 DDECCONT1F Address (hex): 1Fh Reset Value (bin): 0001 1000 Bit ...
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Register List Bit Name Bits [7:6] Reserved: Must be set to 00. Bits [5:4] Reserved: Must be set to 00. Bits [3:2] Reserved: Must be set to 01. Bits [1:0] Reserved: Must be set to 00. DDECCONT21 Address (hex): 21h ...
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STV2310 Bit Name HSYNCSHIFT_D This register allows a programmable delay of HSYNC output signal. This register is only active when EL[1:0] o_hsyncshift_en is active (see register DDECCONT22[0]). 00: (no details yet) HSYNCSHIFT_E Output Synchronisation shift enable delay ...
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Register List Bit Name Bits [7:4] Reserved. Must be set to 1001. HSYNC_SAV HSYNC / SAV This option bit is active when set AND the output mode is an analog mode (see DDECCONT0[7] register). 0: the hsync signal is issued ...
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STV2310 DDECCONT28 Address (hex): 28h Reset Value (bin): 1000 0010 Bit 7 Bit 6 HUNLOCK_LINE_NUM[3:0] Bit Name HUNLOCK_LINE HPLL number/4 of successive err>thresh for hunlock _NUM[3:0] This register is used by the HPLL. It provides the number of successive lines ...
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Register List Bit Name CLAMP_PROP[1: Proportional Gain Selection 0] This register is related to the CVBS clamp regulation algorithm where a PID filter is used. CLAMP_PROP defines the Proportional Gain selection. 00: Proportional Gain divided by 64 01: Proportional Gain ...
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STV2310 DDECCONT2D Address (hex): 2Dh Reset Value (bin): 0000 1010 Bit 7 Bit 6 Bit Name Bit 7 Reserved: Must be set to 0. Bit 6 Reserved: Must be set to 0. Bits [5:0] Reserved: Must be set to 00 ...
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Register List Bit Name Bit 7 Reserved: Must be set to 0. Bits [6:5] Reserved: Must be set to 00. OVERDRIVE_MO This bit is used for a special proprietary mode between the STV2310 and the STV3500 called DE ...
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STV2310 DDECCONT32 Address (hex): 32h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit Name Bits [7:4] Reserved. Must be set to 0000. Bits [3:0] Reserved. Must be set to 0000. DDECCONT33 Address (hex): 33h Reset Value (bin): 0000 ...
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Register List DDECCONT35 Address (hex): 35h Reset Value (bin): 0000 0000 Bit 7 Bit 6 PLLLOCKIT RGBADJUS _EN T_EN Bit Name PLLLOCKIT_EN PLLLOCK Pad IT Enable 0: The PLLLOCK pad use is determined by the DDECCONT7 register 1: The PLLLOCK ...
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STV2310 DDECCONT37 Address (hex): 37h Reset Value (bin): 1111 1111 Bit 7 Bit 6 CB_SCALING[1:0] Bit Name CB_SCALING 2 LSB for Scaling Factor for Cb data flow [1:0] The Cb data flow in the COR block is multiplied by the ...
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Register List Bit Name CB_SCALING 4 MSBs for Scaling Factor for Cb data flow [5:2] DDECCONT39 Address (hex): 39h Reset Value (bin): 0101 0101 Bit 7 Bit 6 Bit Name Bits [7:0] Reserved. Must be set to 0101 0101. DDECCONT3A ...
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STV2310 DDECCONT3C Address (hex): 3Ch Reset Value (bin): 1111 1100 Bit 7 Bit 6 VSYNCNST TRICKDET_ INTERDET_ D_MASK MASK MASK Bit Name VSYNCNSTD_ Mask for interruption on change of status on VSYNCLOC_NSTD. MASK 0: Interrupt is not masked TRICKDET_ Mask ...
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Register List VBICONT2 Address (hex): 3Eh Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit Name Bits[7:6] Reserved. Must be set to 00. SLFIL[5:0] Bitfield Description Filler value used by the STV2310 for coding the filler byte in the ...
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STV2310 VBICONT4 Address (hex): 40h Reset Value (bin): 0010 0111 Bit 7 Bit 6 Bit Name FRAMINGCODE[ New Frame Code Value 7:0] VBICONT5 Address (hex): 41h Reset Value (bin): 1100 0101 Bit 7 Bit 6 WSSF1ONL VPS1ONLY_ Y_EN EN Bit ...
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Register List VBICONT6 Address (hex): 42h Reset Value (bin): 0000 0000 Bit 7 Bit 6 GMVBILINE GMRELAX_ S Bit Name GMVBILINES GM VBI Slicing Enable 0: Data slicing is active on line 21 in 60Hz and line 22 in 50Hz ...
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STV2310 Bit Name Bits [1:0] Reserved. Must be set to 00. Bits [4:2] Reserved. Must be set to 010. Bits [7:5] Reserved. Must be set to 000. VBICONT9 Address (hex): 45h Reset Value (bin): 0110 0011 Bit 7 Bit 6 ...
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Register List Bit Name Bits[4:3] Reserved. Must be set to 00. Bit 2 Reserved. Must be set to 1. Bit 1 Reserved. Must be set to 1. Bit 0 Reserved. Must be set to 0. VBICONT0C Address (hex): 48h Reset ...
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STV2310 VBICONT0F Address (hex): 4Bh Reset Value (bin): 1011 0011 Bit 7 Bit 6 CGSEW[2:0] Bit Name CGSEW[2:0] Interval width for the shift compansation CGNBS[1:0] Number of sample rate for a bit "10" for 1 sample keep every 3 CGNBI[2:0] ...
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Register List VBICONT12 Address (hex): 4Eh Reset Value (bin): 0000 1100 Bit 7 Bit 6 Bit Name Bit 7 Reserved. Must be set to 0. Bit 6 Reserved. Must be set to 0. Bits [5:0] Reserved. Must be set to ...
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STV2310 VBICONT15 Address (hex): 51h Reset Value (bin): 0001 0101 Bit 7 Bit 6 Bit Name Bits [7:0] Reserved. Must be set to 0001 0101. VBICONT16 Address (hex): 52h Reset Value (bin): 1010 0000 Bit 7 Bit 6 EQZPRGM EQZORDER ...
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Register List Bit Name VBI_EQUALCOE These bits select precomputed coefficients for the equaliser or let the equaliser select automatically the FF[2:0] best set of coefficients or impose to the equaliser the sets of coefficients programmed 000: use set 1 of ...
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STV2310 Bit Name INTERDET_ACK Acknowledge for interrupt on INTERLACED_DETECTED status change VCRDET_ACK Acknowledge for interrupt on VCR_DETECTED status change INSERDET_ACK Acknowledge for interrupt on INSER_DETECTED status change FBDET_ACK Acknowledge for interrupt on FB_DETECTED status change PLLLOCK_ACK Acknowledge for interrupt on ...
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Register List DDECSTAT2 Address (hex): 81h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 VLOCK HLOCK PLLLOCK Bit Name VLOCK Flag used to signal Vertical Synchronization Signal Capture 0: Vsync is not captured HLOCK Flag used to ...
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STV2310 Bit Name INSER_ When set, this bit indicates that a transition on the FB signal has been detected inside an active line at least DETECTED once in the field. This flag remains set for the next field. FB_DETECTED When ...
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Register List Bit Name SLFIL[7:0] Reserved. DDECSTAT7 Address (hex): 86h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 GEM_DETE Bit Name Bit 7 Reserved. Bit 6 Reserved. GEM_DETECTE Detection of gemstar ancillary data D CC_DETECTED Detection of ...
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STV2310 6 Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol V 3.3 V Supply Voltage 3.3V V 1.8 V Supply Voltage 1.8V V Capacitor 100 pF discharged via 1.5 kΩ serial resistance ESD (Human Body Model) T Operating Temperature OPER T ...
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Electrical Characteristics Symbol V C Full Scale Input Voltage (before external Anti-Aliasing Filter IN_Chroma with Attenuation = 0.55) C Input Coupling Capacitor for CVBS IN_CVBS C Input Coupling Capacitor for C IN_C BW Input Bandwidth Analog Input CVBS CL CVBS/Y ...
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STV2310 6.6 FB Input Symbol V FB Input Voltage Low Level Input Voltage High Level Input Leakage Current L 6.7 Analog-to-Digital Converter (ADC) Symbol 10-bit ADC for CVBS Input B Analog Bandwidth f ADC ...
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Electrical Characteristics Symbol t Fall Time f Maximum Capacitive Load 6.10 Clock Data Output Symbol V Low Level Output Voltage ( High Level Output Voltage ( Rise Time r t Fall Time f Maximum Capacitive Load ...
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STV2310 Symbol f Crystal Frequency, Fundamental Mode XTAL R Internal Bias Resistance BIAS Tolerance (including Temp. shift) Parameter Electrical Characteristics Min. Typ. Max Unit 27 MHz 1.5 MΩ ±60 ppm 105/113 ...
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Electrical Characteristics 6.13 Horizontal/Vertical Synchronization Block Symbol Output Luma/Sync Misalignment Output Chroma/Sync Misalignment Line PLL Capture Range 6.14 Chroma Block Symbol ACC Control Range Chroma PLL Capture Range Total Chroma Phase Tracking Error Quadrature Error Hue Control Range Hue Control ...
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STV2310 Symbol Parameter C Load Capacitance L C Input Capacitance I I²C Timing t Clock Low period LOW t Clock High period HIGH t Data Set-up Time SU,DAT t Data Hold Time HD,DAT t Set-up Time from Clock High SU,STO ...
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Package Mechanical Data 7 Package Mechanical Data 7.1 TQFP64 14x14 Package 108/113 Figure 20: TQFP64 14x14 Package Figure 21: 64-Pin Thin Quad Flat Package Dim. 0.10mm .004 seating plane ...
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STV2310 7.2 TQFP64 10x10 Package 7.3 Lead-free Packaging To meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on ...
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Revision History 8 Revision History The following table summarizes the modifications applied to this document. Revision 1.0 First Issue Section 5.3: VBI Control Register Descriptions on page 87 1.1 Addition of Chapter 7: Package Mechanical Data on page 108 1.2 ...
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STV2310 Revision 3.1 Minor updates to Register Description 4.0 Section 7.3 added, disclaimer updated. Technical content unaffected. Description Revision History Date December 2004 07-Nov-2008 111/113 ...
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A A/D Converter ................................................ 6, 15 Adaptive Time Constant .................................... 16 Alpha Blending .................................................. 24 Anti-Aliasing Filter .............................................. 15 Automatic Flesh Control .................................... 23 Automatic Gain Control ...................................... 14 C CCIR Specification ................................... 6, 25, 42 Chroma Demodulator .................................. 21, ...
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... STV2310 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...