74HC4053N NXP Semiconductors, 74HC4053N Datasheet - Page 9

• Manufacturer Part Number: 74HC4053N
• Description: Analog Multiplexer Triple 2:1 16-Pin PDIP Bulk
• Manufacturer: NXP Semiconductors
• Type: Analog Multiplexerr

Specifications of 74HC4053N

• Package: 16PDIP
• Maximum On Resistance: 180@4.5V Ohm
• Maximum Propagation Delay Bus To Bus: 60@2V|12@4.5V|10@6V|8@±4.5V ns
• Maximum Low Level Output Current: 25 mA
• Multiplexer Architecture: 2:1
• Maximum Turn-off Time: 210@2V ns
• Maximum Turn-on Time: 220@2V ns
• Power Supply Type: Single|Dual
• Logic Type: Multiplexer / Demultiplexer
• No. Of Outputs: 6
• Supply Voltage Range: 2V To 6V
• Logic Case Style: DIP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Base Number: 74
• Rohs Compliant: Yes

Philips Semiconductors
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
Note to HCT types
1. The value of additional quiescent supply current ( I
December 1990
V
V
I
INPUT
S
E
SYMBOL
CC
I
I
I
I
I
IH
IL
n
Triple 2-channel analog
multiplexer/demultiplexer
I
S
S
S
CC
To determine I
UNIT LOAD COEFFICIENT
0.50
0.50
HIGH level input
voltage
LOW level input
voltage
input leakage
current
analog switch
OFF-state
current per
channel
analog switch
OFF-state
current all
channels
analog switch
ON-state current
quiescent supply
current
additional
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
PARAMETER
CC
per input, multiply this value by the unit load coefficient shown in the table below.
2.0
min.
1.6
1.2
100
+25
typ.
0.8
0.1
0.1
0.1
0.1
8.0
16.0
360
max. min.
T
74HCT
amb
2.0
40 to +85
CC
( C)
) for a unit load of 1 is given here.
0.8
1.0
1.0
1.0
1.0
80.0
160.0
450
max.
9
2.0
min.
40 to +125
0.8
1.0
1.0
1.0
1.0
160.0
320.0
490
max.
V
V
UNIT
A
A
A
A
A
A
4.5
to
5.5
4.5
to
5.5
5.5
10.0
10.0
10.0
5.5
5.0
4.5
to
5.5
V
(V)
CC
74HC/HCT4053
TEST CONDITIONS
0
0
0
0
0
0
V
(V)
5.0
EE
Product specification
V
or
GND
V
or
V
V
or
V
V
or
V
V
or
GND
V
V
2.1
CC
CC
V
IH
IL
IH
IL
IH
IL
CC
I
V
Fig.10
V
Fig.10
V
Fig.11
V
or V
V
or V
other
inputs
at V
GND
V
V
V
CC
CC
CC
is
OS
OTHER
S
S
S
= V
CC
EE
CC
= V
=
=
=
V
V
V
;
EE
or
EE
EE
EE
CC