PRIXP422ABB Intel, PRIXP422ABB Datasheet - Page 38

• Manufacturer Part Number: PRIXP422ABB
• Description: Network Proc 1.3V/3.3V 266MHz 492-Pin BGA
• Manufacturer: Intel

Specifications of PRIXP422ABB

• Package: 492BGA
• Core Operating Frequency: 266 MHz
• Operating Supply Voltage: 1.3|3.3 V
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Signal Descriptions
Table 11.
June 2007
38
MII Interfaces (Sheet 1 of 2)
ETH_TXCLK0
ETH_TXDATA0[3:0]
ETH_TXEN0
ETH_RXCLK0
ETH_RXDATA0[3:0]
ETH_RXDV0
ETH_COL0
ETH_CRS0
ETH_MDIO
ETH_MDC
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Reset
Post
VI
VI
VI
VI
VI
VI
Z
Z
0
0
Type
I/O
IO
O
O
I
I
I
I
I
I
Table 5 on page
†
Externally supplied transmit clock.
Should be pulled high
Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK0.
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted synchronously, with
respect to ETH_TXCLK0, at the first nibble of the preamble and remains asserted until all the nibbles of a
frame are presented.
Externally supplied receive clock.
Should be pulled high
Receive data bus from PHY, data sampled synchronously with respect to ETH_RXCLK0
Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. Should be pulled
high
Asserted by the PHY when a collision is detected by the PHY. Should be pulled low through a 10-KΩ resistor
when not being utilized in the system.
Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when both the
transmit and receive medium are idle. Remains asserted throughout the duration of a collision condition. PHY
asserts CRS asynchronously and de-asserts synchronously, with respect to ETH_RXCLK0. Should be pulled
high
Management data output. Provides the write data to both PHY devices connected to each MII interface.
An external 1.5-KΩ pull-up resistor is required.
Note:
Should be pulled high
Management data clock. Management data interface clock is used to clock the MDIO signal as an output and
sample the MDIO as an input. The ETH_MDC is an input on power up and can be configured to be an output
through an Intel API as documented in the Intel
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• Should be pulled high
††
††
through a 10-KΩ resistor when not being utilized in the system.
through a 10-KΩ resistor when not being utilized in the system.
If interfacing with a single Intel
used, the NPE will ‘see’ 32 PHYs on the MII interface.
30.
††
††
††
through a 10-KΩ resistor when not being utilized in the system.
through a 10-KΩ resistor when not being utilized in the system.
through a 10-KΩ resistor when not being utilized in the system.
††
through a 10-KΩ resistor when not being utilized in the system.
Intel
®
IXP45X and Intel
®
LXT972 Fast Ethernet Transceiver, and a 1.5K pull-up resistor is not
®
Description
IXP400 Software Programmer’s Guide.
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US