SCC68681C1A44 NXP Semiconductors, SCC68681C1A44 Datasheet
SCC68681C1A44
Specifications of SCC68681C1A44
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SCC68681C1A44 Summary of contents
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... SCC68681 Dual asynchronous receiver/transmitter (DUART) Product data INTEGRATED CIRCUITS 2004 Apr 06 ...
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... Non-standard user-defined rate derived from programmable counter/timer – External clock ORDERING INFORMATION Package Type number Name Description Commercial 5 + amb SCC68681C1A44 PLCC44 plastic leaded chip carrier; 44 leads SCC68681C1N40 DIP40 plastic dual in-line package; 40 leads (600 mil) Industrial 10 – + amb SCC68681E1A44 PLCC44 plastic leaded chip carrier ...
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... Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. IACKN Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending. 2004 Apr ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) SYMBOL SYMBOL PIN TYPE TYPE PLCC44 DIP40 X1/CLK Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 8, Clock Timing. ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM 8 D0–D7 BUS BUFFER OPERATION CONTROL R/WN DTACKN ADDRESS DECODE CSN 4 A1–A4 R/W CONTROL RESETN INTERRUPT CONTROL INTRN IMR ISR IACKN IVR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER X1/CLK XTAL OSC ...
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... X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART external is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 8. ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) address 0xF with the accompanying data specifying the bits to be reset (1 = reset change). Outputs can be also individually assigned specific functions by appropriate programming of the Channel A mode registers (MR1A, MR2A), the Channel B mode registers (MR1B, MR2B), and the Output Port Configuration Register (OPCR) ...
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... SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled. PROGRAMMING The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats BIT 7 BIT 6 RxRTS RxINT CONTROL SELECT MR1A MR1A MR1B RxRDY 1 = Yes 1 = FFULL NOTE block error mode, block error conditions must be cleared by using the error reset command (command 4x receiver reset. ** Please see Receiver Reset note on page 19. ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats (Continued) BIT 7 BIT 6 BRG SET ACR SELECT MODE AND SOURCE 0 = set set 2 BIT 7 BIT 6 DELTA DELTA IPCR IP3 IP2 Yes 1 = Yes BIT 7 BIT 6 INPUT DELTA PORT ISR BREAK B CHANGE Yes 1 = Yes ...
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... MR1A. Accesses to MR2A do not change the pointer. MR2A[7:6] – Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7: the normal mode, with the transmitter and receiver operating independently. MR2A[7: places the channel in the automatic echo mode, which automatically re-transmits the received data ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) commands issued via the SOPR and ROPR registers. MR2[5] set to 1 caused the RTSN to be reset automatically one bit time after the character(s) in the transmit shift register and in the THR (if any) are completely transmitted (including the programmed number of stop bits previously issued transmitter disable is pending ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) CSRB – Channel B Clock Select Register CSRB[7:4] – Channel B Receiver Clock Select This field selects the baud rate clock for the Channel B receiver. The field definition is as shown in Table 3, except as follows: Baud Rate CSRB[7:4] CSRB[7:4] ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) SRA[4] – Channel A Overrun Error This bit, when set, indicates that one or more characters in the received data stream have been lost set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position ...
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... Duty cycle of 16 clock is 50% 1%. Rates will change in direct proportion to to the X1 rate of 3.6864 MHz. Asynchronous UART communications can tolerate frequency error of 4. ‘clean’ communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit ...
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... ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 00 when the DUART is reset. 16 ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0] ...
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... CTUR and CTLR. IVR – Interrupt Vector Register This register contains the interrupt vector. The register is initialized to H‘0F’ by RESET. The contents of the register are placed on the data bus when the DUART responds to a valid interrupt acknowledge cycle. 17 Product data ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Output Port Notes The output ports are controlled from three places: the OPCR register, the OPR register, and the MR registers. The default source of data for the OP[7:0] pins is the OPR register. When the OPR is the source for the OP pins, the pins will drive the complement (inverse) of data in the OPR register ...
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... Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1 ABSOLUTE MAXIMUM RATINGS SYMBOL T Operating ambient temperature range amb T Storage temperature range stg All voltages with respect to ground Maximum pin voltages NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART CHARACTERISTICS T = – + 5.0 V 10% amb CC SYMBOL SYMBOL Reset Timing (See Figure 3) t RESETN pulse width RES Bus Timing (See Figures A1–A4 setup time to CSN LOW AS t A1–A4 hold time from CSN LOW AH t RWN setup time to CSN HIGH ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) RESETN t RES Figure 3. Reset Timing X1/CLK A1–A4 RWN CSN D0–D7 DTACKN X1/CLK A1–A4 RWN CSN D0–D7 DTACKN NOTE: DACKN requires two rising edges of X1 clock after CEN is low. 2004 Apr 06 SD00109 t CSC RWS CSW t DD ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) X1/CLK INTRN IACKN D0–D7 DTACKN CSN IP0–IP5 CSN OP0–OP7 2004 Apr 06 t CSC CSD t DAL t t DCR DAH t DAT Figure 6. Interrupt Cycle Timing OLD DATA t PD Figure 7. Port Timing 23 Product data SCC68681 t DF ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) t CLK t CTC X1/CLK CTCLK RxC TxC FOR NOTE: C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE INCLUDED WITH C1 AND C2 ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS FREQUENCY: LOAD CAPACITANCE (C TYPE OF OPERATION: NOTES: 1. INTRN or OP3 – ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TxC (INPUT) TxC (1X OUTPUT) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) CSN (WRITE CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 2004 Apr 06 1 BIT TIME ( CLOCKS) t TXD ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP4) CSN (READ) STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR(4) and MR1( MASTER STATION ADD#1 TxD TRANSMITTER ENABLED ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2004 Apr 06 27 Product data SCC68681 SOT187-2 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 2004 Apr 06 28 Product data SCC68681 SOT129-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) REVISION HISTORY Rev Date Description _1 20040406 Product data (9397 750 12079). ECN 853-2447 01-A15014 of 15 December 2003. Data sheet status Product [1] Level Data sheet status [2] [3] status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design ...