SI2493-C-FT Silicon Laboratories Inc, SI2493-C-FT Datasheet - Page 56

• Manufacturer Part Number: SI2493-C-FT
• Description: 56 KBPS, V.92 ISOMODEM SYSTEM-SIDE - LEAD-FREE TSSOP 0 TO 7
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN93
3.1.11. Sleep Mode
The Si2493/57/34/15/04 can be set to enter a low-
power sleep mode when not connected and after a
period of inactivity determined by the S24 register.
The Si2493/57/34/15/04 enters the sleep mode S24
seconds after the last DTE activity, after the TX FIFO is
empty, and after the last data is received from the
remote modem. The Si2493/57/34/15/04 returns to the
active mode when there is a 1 to 0 transition on TXD in
the serial mode or a 1 to 0 transition on CS in the
parallel mode or if an incoming ring is detected. The
delay range for S24 is 1 to 255 seconds. The default
setting of S24 = 0 disables the sleep timer and keeps
the modem in the normal power mode regardless of
activity level.
3.1.12. Powerdown
The powerdown mode is a lower power state than sleep
mode but is entered immediately upon writing
U65[13] (PDN) = 1. Once in the powerdown mode, the
modem requires a hardware reset via the RESET pin
(Si2493/57/34/15/04, pin 12) to become active.
3.1.13. Reset/Default Settings
The modem must be reset after power is stable and
prior to the first “AT” command. The reset pin (Si2493/
57/34/15/04, pin 12) must be asserted at least 5 ms low
to adequately reset the on-chip registers.
56
Rev. 0.9
CTS (pin 11) must remain at a Logic 1 (high state)
during Reset. The internal pull-up resistor is adequate
for most applications. If leakage or transients are
present on CTS during Reset, the high value internal
resistor should be supplemented with an external 10 kΩ
resistor to V
Autobaud is enabled on the DTE by default. A 10 kΩ
resistor connected from EESD/D2 (Si2493/57/34/15/04
pin 18) to GND (Si2493/57/34/15/04 pin 20) disables
autobaud on powerup or reset and forces 19.2 kbps.
Serial or parallel interface selection depends upon the
state of Si2493/57/34/15/04, pin 15, AOUT/INT, at the
rising edge of the reset pulse. If AOUT/INT is left open,
an internal pullup resistor holds the pin at a logic 1, and
the serial interface is selected (default). If AOUT/INT is
connected to ground through a 10 kΩ resistor, the
parallel interface is selected.
A 10 kΩ resistor between D6 (Si2493/57/34/15/04 pin 4)
and GND (Si2493/57/34/15/04 pin 20) enables the
EEPROM interface on powerup or reset. Table 24
summarizes the options for enabling features on
powerup and reset by connecting a 10 kΩ resistor
between the indicated Si2493/57/34/15/04 pin and GND
(Si2493/57/34/15/04 Pin20). Zeroes indicate a <10 kΩ
pulldown to ground at startup or reset; “1”s indicate
internal pullup (do not pull down externally), and “X”s
indicate a don’t care.
CC
.