SI2493-C-FT Silicon Laboratories Inc, SI2493-C-FT Datasheet - Page 72

• Manufacturer Part Number: SI2493-C-FT
• Description: 56 KBPS, V.92 ISOMODEM SYSTEM-SIDE - LEAD-FREE TSSOP 0 TO 7
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN93
72
Register Address
U4E
U6A
U6C
U6E
U7A
U7C
U7D
U4F
U50
U51
U52
U53
U62
U63
U65
U66
U67
U68
U6F
U70
U71
U76
U77
U78
U79
U83
U84
U85
0x006C
0x007C
0x007D
0x004E
0x004F
0x006A
0x006E
0x006F
0x007A
0x0050
0x0051
0x0052
0x0053
0x0062
0x0063
0x0065
0x0066
0x0067
0x0068
0x0070
0x0071
0x0076
0x0077
0x0078
0x0079
0x0083
0x0084
0x0085
(Hex)
DAAC1
DAAC3
DAAC4
DAAC5
PRDD
MOD2
GENA
GENC
GEND
NOLN
Name
LCDN
XMTL
PTME
GEN1
GEN2
GEN3
GEN4
LCDF
NLIU
ITC1
ITC2
ITC4
LIUS
FHT
CK1
LVS
IO0
IO1
Table 32. U-Register Descriptions (Continued)
Pre-dial delay-time—(ms units).
Flash hook time—(ms units).
Loop current debounce on time (ms units).
Loop current debounce off time (ms units).
Transmit level adjust (1 dB units)
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register (read only).
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
No-Line threshold. If %V1 is set, NOLN sets the threshold for
determination of line present vs. line not present. 3 V/bit
Line-in-use threshold. If %V1 is set, LIUS sets the threshold for
determination of line in use vs. line not in use. 3 V/bit
Line-in-use/No line threshold. If %V2 is set, NLIU sets the thresh-
old reference for the adaptive algorithm (see %V2). 3 V/bit
Rev. 0.9
Description
Default
0x00C8
0xXX40
0xXX00
0x00FF
0x00XX
0x0000
0x01F4
0x015E
0x0000
0x0000
0x0804
0x0003
0x00E0
0x0008
0x0000
0x7F20
0x2700
0x0000
0x3240
0x401E
0x0000
0x0000
0x0000
0x0000
0x0001
0x0007
0x0000
Value
N/A