82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 4

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

Table of Contents
4 TYPICAL APPLICATION ................................................................................................................................................. 47
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 48
6 JTAG ................................................................................................................................................................................ 58
7 PROGRAMMING INFORMATION .................................................................................................................................... 59
8 THERMAL MANAGEMENT ........................................................................................................................................... 149
IDT82V3280
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 39
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39
3.14 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 44
3.15 INTERRUPT SUMMARY ............................................................................................................................................................................... 45
3.16 T0 AND T4 SUMMARY ................................................................................................................................................................................. 45
3.17 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 46
4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 47
5.1 EPROM MODE .............................................................................................................................................................................................. 49
5.2 MULTIPLEXED MODE .................................................................................................................................................................................. 50
5.3 INTEL MODE ................................................................................................................................................................................................. 52
5.4 MOTOROLA MODE ...................................................................................................................................................................................... 54
5.5 SERIAL MODE .............................................................................................................................................................................................. 56
7.1 REGISTER MAP ............................................................................................................................................................................................ 59
7.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 65
8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 149
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35
3.11.1 PFD Output Limit ............................................................................................................................................................................ 37
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37
3.13.1 Output Clocks ................................................................................................................................................................................. 39
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 42
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 148
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34
3.10.1.5 Holdover Mode ................................................................................................................................................................. 34
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.2.2 Locked Mode .................................................................................................................................................................... 35
3.10.2.3 Holdover Mode ................................................................................................................................................................. 35
3.11.5.1 T0 Path ............................................................................................................................................................................. 37
3.11.5.2 T4 Path ............................................................................................................................................................................. 38
Global Control Registers ............................................................................................................................................................... 65
Interrupt Registers ......................................................................................................................................................................... 74
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 79
Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 102
T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 116
T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 120
T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 122
Output Configuration Registers .................................................................................................................................................. 136
PBO & Phase Offset Control Registers ...................................................................................................................................... 146
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35
3.10.1.5.4 Manual ........................................................................................................................................................... 35
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35
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December 9, 2008
WAN PLL