82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 64

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

Table 42: Register List and Map (Continued)
Programming Information
IDT82V3280
Address
(Hex)
5B
5C
5D
5E
6A
6B
6C
6D
6E
5F
60
61
62
63
64
65
66
67
68
69
6F
70
PHASE_LOSS_FINE_LIMIT_CNFG -
Phase Loss Fine Detector Limit Con-
figuration *
T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG -
T0 DPLL Holdover Frequency Config-
uration 1
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 3
T4_DPLL_APLL_PATH_CNFG - T4
DPLL & APLL Path Configuration
T4_DPLL_LOCKED_BW_DAMPING_
CNFG - T4 DPLL Locked Bandwidth &
Damping Factor Configuration
CURRENT_DPLL_FREQ[7:0]_STS -
DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS -
DPLL Current Frequency Status 2 *
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS -
DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
OUT2_FREQ_CNFG - Output Clock 2
Frequency Configuration
OUT3_FREQ_CNFG - Output Clock 3
Frequency Configuration
OUT4_FREQ_CNFG - Output Clock 4
Frequency Configuration
OUT5_FREQ_CNFG - Output Clock 5
Frequency Configuration
OUT6_FREQ_CNFG - Output Clock 6
Frequency Configuration
Register Name
-
T_PH_LOS
FREQ_LIM
FINE_PH_
LOS_LIMT
MAN_HOL
T4_DPLL_LOCKED_DAMPING[2:0]
DOVER
Bit 7
_EN
-
FAST_LOS
AUTO_AV
OUT1_PATH_SEL[3:0]
OUT2_PATH_SEL[3:0]
OUT3_PATH_SEL[3:0]
OUT4_PATH_SEL[3:0]
OUT5_PATH_SEL[3:0]
OUT6_PATH_SEL[3:0]
T4_APLL_PATH[3:0]
Output Configuration Registers
Bit 6
_SW
G
-
FAST_AVG
T0_APLL_BW[1:0]
Bit 5
64
-
DPLL_FREQ_HARD_LIMT[15:8]
CURRENT_DPLL_FREQ[23:16]
DPLL_FREQ_HARD_LIMT[7:0]
T0_HOLDOVER_FREQ[23:16]
CURRENT_DPLL_FREQ[15:8]
T0_HOLDOVER_FREQ[15:8]
CURRENT_DPLL_FREQ[7:0]
T0_HOLDOVER_FREQ[7:0]
CURRENT_PH_DATA[15:8]
CURRENT_PH_DATA[7:0]
READ_AV
DPLL_FREQ_SOFT_LIMT[6:0]
Bit 4
G
-
-
T4_GSM_GPS_16E1_1
TEMP_HOLDOVER_M
Bit 3
-
6T1_SEL[1:0]
-
-
ODE[1:0]
OUT1_DIVIDER[3:0]
OUT2_DIVIDER[3:0]
OUT3_DIVIDER[3:0]
OUT4_DIVIDER[3:0]
OUT5_DIVIDER[3:0]
OUT6_DIVIDER[3:0]
Bit 2
-
-
PH_LOS_FINE_LIMT[2:0]
T4_12E1_24T1_E3_T3
T4_DPLL_LOCKED_B
T4_APLL_BW[1:0]
Bit 1
-
_SEL[1:0]
W[1:0]
December 9, 2008
Bit 0
-
WAN PLL
Reference
P 128
P 129
P 129
P 130
P 130
P 131
P 132
P 133
P 133
P 133
P 134
P 134
P 135
P 132
P 132
P 134
P 136
P 137
P 138
P 139
P 140
P 141
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