MT48LC32M16A2P-75 IT:C Micron Technology Inc, MT48LC32M16A2P-75 IT:C Datasheet - Page 24

• Manufacturer Part Number: MT48LC32M16A2P-75 IT:C
• Description: DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M16A2P-75 IT:C

• Density: 512 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 12:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Random READ Accesses
Note:
COMMAND
COMMAND
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 13 on page 25 and
Figure 14 on page 25. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. After the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 14 on page 25, then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
COL n
T0
BANK,
COL n
READ
READ
CL = 2
T1
T1
BANK,
BANK,
READ
READ
COL a
COL a
CL = 3
BANK,
T2
T2
COL x
BANK,
READ
READ
COL x
24
D
OUT
n
T3
T3
BANK,
COL m
READ
READ
BANK,
COL m
D
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
a
OUT
n
Transitioning Data
T4
T4
NOP
NOP
D
D
OUT
x
OUT
a
T5
T5
NOP
NOP
512Mb: x4, x8, x16 SDRAM
D
D
m
OUT
OUT
x
T6
Don’t Care
NOP
D
©2000 Micron Technology, Inc. All rights reserved.
OUT
m
Operations