MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet

IC SDRAM 128MBIT 167MHZ 86TSOP

MT48LC4M32B2P-6:G

Manufacturer Part Number
MT48LC4M32B2P-6:G
Description
IC SDRAM 128MBIT 167MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M32B2P-6:G

Package / Case
86-TSOPII
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
RoHS Compliant
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating Temperature Min
0°C
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Configuration
4 BLK (1M X 32)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Synchronous DRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode (not available on AT devices)
• Auto refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Options
• Configuration
• Package – OCPL
• Timing (cycle time)
• Die revision
• Operating temperature range
Notes: 1. Off-center parting line.
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_1.fm - Rev. L 1/09 EN
edge of system clock
changed every clock cycle
and auto refresh modes
– 64ms, 4,096-cycle refresh (15.6µs/row)
– 16ms, 4,096-cycle refresh (3.9µs/row)
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) lead-free
– 90-ball VFBGA (8mm x 13mm)
– 90-ball VFBGA (8mm x 13mm) lead-free
– 6ns (166 MHz)
– 7ns (143 MHz)
– Commercial (0° to +70°C)
– Industrial (-40° to +85°C)
– Automotive (–40°C to +105°C)
(commercial & industrial)
(automotive)
2. Consult Micron for availability.
Products and specifications discussed herein are subject to change by Micron without notice.
1
Marking
4M32B2
None
AT
TG
B5
F5
-6
-7
:G
IT
P
2
1
www.micron.com/sdram
Table 1:
Table 2:
Table 3:
Notes: 1. FBGA Device
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
MT48LC4M32B2TG
MT48LC4M32B2P
MT48LC4M32B2F5
MT48LC4M32B2B5
Speed
Grade
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Part Number
decoder.
Frequency
166 MHz
143 MHz
Clock
Key Timing Parameters
CL = CAS (READ) latency
Configurations
128Mb (x32) SDRAM Part Numbers
1
1
Access Time
Decoder: www.micron.com/
Cl = 3
5.5ns
5.5ns
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
1 Meg x 32 x 4 banks
Architecture
4K (A0–A11)
4 (BA0, BA1)
4 Meg x 32
256 (A0–A7)
4 Meg x 32
4 Meg x 32
4 Meg x 32
4 Meg x 32
Setup
Time
1.5ns
2ns
4K
Features
Time
Hold
1ns
1ns

Related parts for MT48LC4M32B2P-6:G

MT48LC4M32B2P-6:G Summary of contents

Page 1

... Refresh count Row addressing Bank addressing Column addressing Marking 4M32B2 Table 3: 128Mb (x32) SDRAM Part Numbers TG P Part Number F5 MT48LC4M32B2TG B5 MT48LC4M32B2P MT48LC4M32B2F5 -6 MT48LC4M32B2B5 -7 :G Notes: 1. FBGA Device decoder. None Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 128Mb: x32 SDRAM ...

Page 2

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of Figures Figure 1: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access opera- tion. The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. ...

Page 6

... ADDRESS 14 BA0, BA1 REGISTER 8 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN BANK0 12 BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX MEMORY 4096 LATCH & (4,096 x 256 x 32) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN ...

Page 7

Pin/Ball Assignments and Descriptions Figure 2: Pin Assignment (Top View) 86-Pin TSOP PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Pin/Ball Assignments and Descriptions DQ0 DQ1 4 DQ2 ...

Page 8

Figure 3: 90-Ball VFBGA Pin Assignment (Top View PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Pin/Ball Assignments and Descriptions ...

Page 9

... Address inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A10) and READ/WRITE command (column-address A0–A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (LOW) ...

Page 10

... Address inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW) ...

Page 11

Functional Description In general, this 128Mb SDRAM (1 Meg banks quad-bank DRAM that oper- ates at 3.3V and includes a synchronous interface (all signals are registered on the posi- tive edge of the clock ...

Page 12

Wait at least All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least are allowed. 10. Issue an AUTO REFRESH command. 11. Wait ...

Page 13

Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal effectively selected. All accesses for that burst take ...

Page 14

Table 6: Burst Definition Burst Length Full Page (256) Notes: 1. For A1–A7 select the block-of-two burst; A0 selects the starting column within the block. 2. For A2–A7 select the block-of-four burst; ...

Page 15

CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two or three clocks. If ...

Page 16

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use and/or test modes. The programmed BL applies to both read ...

Page 17

Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Oper- ation section; these tables provide current state/next state information. Table 8: Truth ...

Page 18

... DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. ...

Page 19

A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge ...

Page 20

Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature (AT) devices. BANK/ROW ACTIVATION Before ...

Page 21

Figure 7: Example: Meeting CLK COMMAND t Notes: 1. RCD (MIN) = 20ns, t RCD (MIN) × where x = number of clocks for equation to be true. READs READ bursts are initiated with a READ command, as shown in ...

Page 22

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from ...

Page 23

Figure 10: Consecutive READ Bursts CLK COMMAND ADDRESS CLK COMMAND ADDRESS CLK COMMAND ADDRESS Notes: 1. Each READ command may be to either bank. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev ...

Page 24

Figure 11: Random READ Accesses CLK COMMAND ADDRESS CLK COMMAND ADDRESS CLK COMMAND ADDRESS Notes: 1. Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, ...

Page 25

Figure 12: READ-to-WRITE CLK DQM COMMAND ADDRESS Notes 3is used for illustration. The READ command may be to any bank, and the WRITE com- mand may be to any bank burst of one is used, ...

Page 26

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a PRECHARGE command to the same ...

Page 27

PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length ...

Page 28

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...

Page 29

Figure 17: WRITE Burst CLK COMMAND ADDRESS Notes DQM is LOW. Figure 18: WRITE-to-WRITE CLK COMMAND ADDRESS Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Figure 19: Random WRITE Cycles CLK ...

Page 30

Figure 20: WRITE-to-READ CLK COMMAND ADDRESS Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW for illustration. Data for any WRITE burst may be ...

Page 31

Figure 21: WRITE-to-PRECHARGE CLK CLK ( DQM COMMAND ADDRESS CLK (when DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of ...

Page 32

Figure 23: PRECHARGE Command CLK CKE RAS# CAS# WE# A0-A9, A11 A10 BA0,1 PRECHARGE The PRECHARGE command (Figure 23) is used to deactivate the open row in a partic- ular bank or the open row in all banks. The bank(s) ...

Page 33

Figure 24: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is ...

Page 34

Figure 26: CLOCK SUSPEND During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Notes: 1. For this example greater, and DQM is LOW. Burst READ/Single WRITE The burst read/single write mode is entered ...

Page 35

Figure 27: READ With Auto Precharge Interrupted by a READ Internal States Notes: 1. DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is HIGH prevent D WRITE ...

Page 36

Figure 29: WRITE With Auto Precharge Interrupted by a READ Internal States Notes: 1. DQM is LOW. Figure 30: WRITE With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. ...

Page 37

Table 9: Truth Table – CKE Notes 1–4 apply to the entire table CKE CKE Current State n Power-down Self refresh Clock suspend L H Power-down Self refresh Clock suspend H L All banks idle All banks ...

Page 38

Table 10: Truth Table – Current State Bank n, Command To Bank n Notes 1–6 apply to the entire table Current State CS# RAS# CAS# Any Idle Row ...

Page 39

The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. 6. All states and sequences not shown are illegal or reserved. 7. ...

Page 40

Table 11: Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m Notes 1–6 apply to the entire table; notes appear below and on next page Current State CS# RAS# Any Idle X X Row ...

Page 41

All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. ...

Page 42

Electrical Specifications Stresses greater than those listed Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational ...

Page 43

Table 13: Temperature Limits Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figures 31 ...

Page 44

Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View Test point PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 22.22mm 11.11mm 8.00mm 4.00mm 13.00mm ...

Page 45

Table 15: DC Electrical Characteristics and Operating Conditions Notes 1, 6 apply to the entire table; notes appear on page 48; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input ...

Page 46

Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes apply to the entire table; notes appear on page 48 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup ...

Page 47

Table 19: AC Functional Characteristics Notes apply to the entire table; notes appear on page 48 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable ...

Page 48

Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V. AC can range from 0pF to 6pF with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address ...

Page 49

The clock frequency must remain constant during access or precharge states (READ, WRITE, including data rate. 25. Auto precharge mode only. 26. JEDEC and PC100 specify three clocks 7ns for -7, 6ns for -6. 28. ...

Page 50

Timing Diagrams Figure 33: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...

Page 51

Figure 34: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock ...

Page 52

Figure 35: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM0 A0-A9, A11 ...

Page 53

Figure 36: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...

Page 54

Figure 37: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM0–3 A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active ...

Page 55

Figure 38: Single READ – Without Auto Precharge T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...

Page 56

Figure 39: Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM0– A0–A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...

Page 57

Figure 40: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0– ROW A0–A9, A11 ENABLE AUTO PRECHARGE ROW ...

Page 58

Figure 41: Read – Full-page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS DQM 0– A0–A9, A11 COLUMN ...

Page 59

Figure 42: Read – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...

Page 60

Figure 43: Single Write T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 BA0, BA1 ...

Page 61

Figure 44: Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM0– A0–A9, A11 ROW ROW A10 DISABLE AUTO ...

Page 62

Figure 45: Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP WRITE t CMS DQM 0 A0-A9, A11 COLUMN m ...

Page 63

Figure 46: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM0– COLUMN m 3 ROW A0–A9, A11 t AS ...

Page 64

Figure 47: Write – Full-page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ROW A10 ...

Page 65

Figure 48: Write – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM 0 A0-A9, A11 ROW ROW A10 ...

Page 66

Package Dimensions Figure 49: 86-Pin Plastic TSOP (400 mil) 22.22 ±0.08 0.50 TYP 0. 0.75 PIN # 1.00 PLATED LEAD FINISH: TG (90% Sn, 10% Pb (100% Sn) 0.01 ±0.005 THICK PER SIDE ...

Page 67

Figure 50: 90-Ball VFBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE A 0.10 A 90X Ø0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE- REFLOW DIAMETER IS 0. 0.40 SMD BALL PAD BALL A9 11.20 ±0.10 5.60 ...

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