MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 11

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Initialization
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
1. Simultaneously apply power to V
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
6. Perform a PRECHARGE ALL command.
In general, this 128Mb SDRAM (1 Meg x 32 x 4 banks) is a quad-bank DRAM that oper-
ates at 3.3V and includes a synchronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096
rows by 256 columns by 32-bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (A0–A7) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LMR command.
The recommended power-up sequence for SDRAMs:
compatible.
constraints specified for the clock pin.
or NOP.
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
DD
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
11
DD
and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q.
Functional Description
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM