MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 38

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Write (auto
Row active
Read (auto
precharge
precharge
disabled)
disabled)
Current
State
Any
Idle
Truth Table – Current State Bank n, Command To Bank n
Notes 1–6 apply to the entire table
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS#
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
after
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 10, and according to Table 11 on
page 40.
CAS#
Row active: A row in the bank has been activated, and
precharge enabled:
precharge enabled:
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
Row activating: Starts with registration of an ACTIVE command and ends when
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not
Read: A READ burst has been initiated, with auto precharge disabled, and has not
Write w/auto
Idle: The bank has been precharged, and
Precharging: Starts with registration of a PRECHARGE command and ends when
Read w/auto
WE#
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
bursts/accesses and no register accesses are in progress.
yet terminated or been terminated.
yet terminated or been terminated.
COMMAND (ACTION)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start precharge)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start precharge)
BURST TERMINATE
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
t
is met. Once
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
enabled and ends when
will be in the idle state.
RP is met. Once
Starts with registration of a WRITE command with auto precharge
n-1
38
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
t
t
RP has been met. Once
RP has been met. Once
n
t
is HIGH (see Table 9 on page 37) and
RP has been met.
t
RCD has been met. No data
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
t
RP is met, the bank
RP is met, the bank
Notes
11
10
10
10
10
10
10
7
7
8
8
8
9
t
RCD