MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 30

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 20:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
WRITE-to-READ
Notes:
COMMAND
1. The WRITE command may be to any bank, and the READ command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 20. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued
which the last desired input data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of frequency, in auto precharge mode. In
addition, when truncating a WRITE burst, the DQM signal must be used to mask input
data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in Figure 21 on page 31. Data n + 1 is either the last of a
burst of two or the last desired of a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
precharge will actually begin coincident with the clock-edge (T2 in Figure 21 on page 31)
on a “one-clock”
t
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
W
ADDRESS
R (between T2 and T3 in Figure 21.)
DQM is LOW. CL = 2 for illustration.
CLK
DQ
WRITE
BANK,
COL n
D
T0
n
IN
t
W
n + 1
NOP
T1
D
R and sometime between the first and second clock on a “two-clock”
IN
BANK,
COL b
READ
T2
30
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
D
T4
OUT
b
DON’T CARE
NOP
b + 1
T5
D
OUT
t
W
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
R after the clock edge at
RP is met. The