MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 35

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 27:
Figure 28:
WRITE with Auto Precharge
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
READ With Auto Precharge Interrupted by a READ
READ With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
2. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
3. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is HIGH at T2 to prevent D
Internal
States
Internal
States
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 29 on page 36).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 30 on page 36).
t
COMMAND
COMMAND
W
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
R is met, where
DQM
CLK
CLK
DQ
DQ
1
Active
Page
READ - AP
BANK n,
BANK n
Page Active
COL a
T0
NOP
T0
READ with Burst of 4
READ - AP
BANK n,
Page Active
Page Active
BANK n
COL a
T1
T1
NOP
CL = 3 (BANK n)
t
W
READ with Burst of 4
R begins when the WRITE to bank m is registered. The last
35
CL = 3 (BANK n)
T2
T2
OUT
NOP
NOP
a + 1 from contending with D
READ - AP
BANK m,
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
BANK m
T3
W
COL d
D
NOP
OUT
a
Interrupt Burst, Precharge
R is met, where
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
d
CL = 3 (BANK m)
IN
Interrupt Burst, Precharge
D
WRITE with Burst of 4
OUT
a
t
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
t
W
R begins when the READ to
T6
T6
d + 2
NOP
NOP
D
IN
D
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
OUT
d
Register Definition
IN
DON’T CARE
DON’T CARE
d at T4.
Idle
T7
T7
t WR - BANK m
d + 3
NOP
NOP
D
t RP - BANK m
IN
Precharge
D
Write-Back
d + 1
OUT
Idle