MT46V64M8P-6T:F Micron Technology Inc, MT46V64M8P-6T:F Datasheet

IC DDR SDRAM 512MBIT 6NS 66TSOP

MT46V64M8P-6T:F

Manufacturer Part Number
MT46V64M8P-6T:F
Description
IC DDR SDRAM 512MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46V64M8P-6T:F

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (64M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
175mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46V64M8P-6T:F
Manufacturer:
MICRON
Quantity:
6 538
Part Number:
MT46V64M8P-6T:F
Manufacturer:
IR
Quantity:
8 000
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
• V
• V
• Bidirectional data strobe (DQS) transmitted/
• Internal, pipelined double-data-rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
• Self refresh (not available on AT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
Table 1:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
architecture; two data accesses per clock cycle
aligned with data for WRITEs
(x16 has two – one per byte)
– 64ms, 8192-cycle(Commercial and industrial)
– 16ms, 8192-cycle (Automotive)
t
RAS lockout supported (
-75E/-75Z
DD
DD
Speed
Grade
-5B
-75
6T
-6
= +2.5V ±0.2V, V
= +2.6V ±0.1V, V
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
CL = 2
133
133
133
133
100
DD
DD
Q = +2.5V ±0.2V
Q = +2.6V ±0.1V (DDR400)
t
RAP =
Clock Rate (MHz)
t
RCD)
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
1
Notes: 1. End of life.
Options
• Configuration
• Plastic package
• Timing – cycle time
• Self refresh
• Temperature rating
• Revision
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 66-pin TSOP
– 66-pin TSOP (Pb-free)
– 60-ball FBGA (10mm x 12.5mm)
– 60-ball FBGA (10mm x 12.5mm) (Pb-free)
– 5ns @ CL = 3 (DDR400B)
– 6ns @ CL = 2.5 (DDR333) (FBGA only)
– 6ns @ CL = 2.5 (DDR333) (TSOP only)
– 7.5ns @ CL = 2 (DDR266)
– 7.5ns @ CL = 2 (DDR266A)
– 7.5ns @ CL = 2.5 (DDR266B)
– Standard
– Low-power self refresh
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
– x4, x8
– x4, x8, x16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Data-Out
Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
512Mb: x4, x8, x16 DDR SDRAM
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
Access
©2000 Micron Technology, Inc. All rights reserved.
DQS–DQ
Marking
Features
+0.40ns
+0.40ns
+0.45ns
+0.50ns
+0.50ns
Skew
128M4
32M16
64M8
-75E
-75Z
None
None
-75
-5B
-6T
BN
:D
TG
FN
AT
IT
-6
:F
P
L
1
1
1
1

Related parts for MT46V64M8P-6T:F

MT46V64M8P-6T:F Summary of contents

Page 1

Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg banks MT46V64M8 – 16 Meg banks MT46V32M16 – 8 Meg banks Features • +2.5V ±0.2V ...

Page 2

Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) 1 Yes -5B – -6 – -6T – -75E ...

Page 3

Table of Contents State Diagram ...

Page 4

State Diagram Figure 2: Simplified State Diagram Power applied Note: This diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. N; Core DDR ...

Page 5

... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock (CK and CK#) ...

Page 6

Automotive Tempature The automotive temperature (AT) option adheres to the following specifications: • 16ms refresh rate • Self refresh not supported • Ambient and case temperatures cannot be less than –40°C or greater than +105°C PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - ...

Page 7

... Functional Block Diagrams The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a 4-bank DRAM. Figure 3: 128 Meg x 4 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTERS COUNTER 15 13 A0–A12, ADDRESS ...

Page 8

... GENERATOR COL0 INPUT 16 REGISTERS 1 1 MASK 1 1 WRITE 16 2 FIFO & DRIVERS Out In DATA CK COL0 BANK3 BANK2 BANK1 BANK0 MEMORY ARRAY DATA READ MUX LATCH 16 2 DQS 16384 GENERATOR COL0 INPUT 32 REGISTERS 2 2 MASK 2 2 WRITE 4 32 512 FIFO (x32) & ...

Page 9

Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignment (Top View DQ0 DQ1 ...

Page 10

Figure 7: 60-Ball FBGA Ball Assignment (Top View REF REF DQ14 DQ12 DQ10 DQ8 V REF PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D2.fm - ...

Page 11

... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...

Page 12

Table 4: Pin and Ball Descriptions (continued) FBGA TSOP Numbers Numbers Symbol E3 51 DQS E7 16 LDQS E3 51 UDQS V F8 B2, D2, C8 15, 55, DD E8, ...

Page 13

Package Dimensions Figure 8: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold ...

Page 14

Figure 9: 60-Ball FBGA (10mm x 12.5mm) 0.85 ±0.05 SEATING PLANE C 0.10 C .45 60X Ø 0.80 (TYP) SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40. BALL A9 11.00 5.50 ±0.05 3.20 ±0.05 ...

Page 15

Electrical Specifications – I Table 6: I Specifications and Conditions (x4, x8 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 8 ...

Page 16

Table 7: I Specifications and Conditions (x16 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 8 on page 17 A Parameter/Condition ...

Page 17

Table 8: I Test Cycle Times DD Values reflect number of clock cycles for each test Speed Clock Cycle I Test Grade Time -75/75Z 7.5ns DD -75E 7.5ns -6/-6T 6ns -5B 5ns I 1 -75 7.5ns DD ...

Page 18

Electrical Specifications – DC and AC Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above ...

Page 19

Table 11: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) Notes: 1–5, 17 apply to the entire table; Notes appear on page 35; V Parameter/Condition Supply voltage I/O supply voltage I/O reference voltage I/O termination voltage (system) ...

Page 20

Figure 10: Input Voltage Waveform Transmitter Notes Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR ...

Page 21

Table 13: Clock Input Operating Conditions Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Parameter/Condition Clock input mid-point voltage: CK and CK# Clock input voltage ...

Page 22

Table 14: Capacitance (x4, x8 TSOP) Note: 14 applies to the entire table; Notes appear on page 35 Parameter Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQ, ...

Page 23

Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 24

Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) (continued) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Write recovery time Internal ...

Page 25

Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 26

Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...

Page 27

Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 28

Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...

Page 29

Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 30

Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...

Page 31

Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 32

Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...

Page 33

Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...

Page 34

Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...

Page 35

Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output ...

Page 36

The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 17. Inputs are not recognized as valid until ...

Page 37

The input capacitance per pin group will not differ by more than this maximum amount for any given device. 31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). Figure 12: Derating Data ...

Page 38

The full driver pull-up current variation from MIN to MAX process; temperature 38d. The driver pull-up current variation within nominal limits of voltage and temper- 38e. The full ratio variation of MAX to MIN pull-up and pull-down current should ...

Page 39

The driver pull-up current variation, within nominal voltage and temperature 39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should 39f. The full ratio variation of the nominal pull-up to pull-down current should be Figure 15: ...

Page 40

RPST end point and but specify when the device output is no longer driving ( t ( RPRE). 45. During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the ...

Page 41

Table 26: Normal Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 ...

Page 42

Table 27: Reduced Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 ...

Page 43

Commands Tables 28 and 29 provide a quick reference of available commands. Two additional Truth Tables—Table 30 on page 44 and Table 31 on page 45—provide current state/next state information. Table 28: Truth Table 1 – Commands CKE is HIGH ...

Page 44

Table 30: Truth Table 3 – Current State Bank n – Command to Bank n Notes: 1–6 apply to the entire table; Notes appear below Current State CS# RAS# CAS# Any Idle L L Row active L ...

Page 45

Refreshing: Starts with registration of an AUTO REFRESH command and ends when • Accessing mode register: Starts with registration of an LMR command and ends when • Precharging all: Starts with registration of a PRECHARGE ALL command and ends ...

Page 46

This table describes alternate bank operation, except where noted (that is, the current state is for bank n, and the commands shown are those allowed to be issued to bank m, assuming that bank such a ...

Page 47

Table 33: Truth Table 5 – CKE Notes 1–6 apply to the entire table; Notes appear below CKE CKE Current State n Power-down Self refresh L H Power-down Self refresh H L All banks idle Bank(s) active ...

Page 48

ACTIVE (ACT) The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in Figure 17. The value on the BA0, BA1 inputs selects ...

Page 49

READ The READ command is used to initiate a burst read access to an active row, as shown in Figure 18 on page 49. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs ...

Page 50

WRITE The WRITE command is used to initiate a burst write access to an active row as shown in Figure 19. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai and configuration, ...

Page 51

PRECHARGE (PRE) The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks as shown in Figure 20. The value on the BA0, BA1 inputs selects the bank, and the ...

Page 52

Operations INITIALIZATION Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described ...

Page 53

Figure 21: INITIALIZATION Flow Diagram Step PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B ...

Page 54

Figure 22: INITIALIZATION Timing Diagram ( ( ) ) VTD REF ) ) ( ( CK ...

Page 55

... A8, which is self- clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation ...

Page 56

Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 23 on page 55. The burst length determines the maximum ...

Page 57

CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set (-5B only) ...

Page 58

Table 35: CAS Latency Speed -5B -6/-6T -75E -75Z -75 Operating Mode The normal operating mode is selected by issuing an LMR command with bits A7–An each set to zero and bits A0–A6 set to the desired values. A DLL ...

Page 59

Figure 25: Extended Mode Register Definition Notes the most significant row address bit from Table 2 on page 2. 2. The QFC# option is not supported. ACTIVE After a row ...

Page 60

Figure 26: Example: Meeting T0 T1 CK# CK Command ACT NOP Row Address Bank x BA0, BA1 READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, ...

Page 61

Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 31 on page 66. The BURST TERMINATE latency is equal to the CL, that is, the BURST TERMINATE command should be issued x ...

Page 62

Figure 27: READ Burst T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ ...

Page 63

Figure 28: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...

Page 64

Figure 29: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...

Page 65

Figure 30: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...

Page 66

Figure 31: Terminating a READ Burst T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n ...

Page 67

Figure 32: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS CK# CK READ Command Bank a, Address Col n DQS DQ DM ...

Page 68

Figure 33: READ-to-PRECHARGE T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ Notes: ...

Page 69

Figure 34: Bank READ – Without Auto Precharge CKE Command NOP ACT Row Address A10 Row BA0, ...

Page 70

Figure 35: x4, x8 Data Output Timing – DQ (first data no longer valid) DQ (first data no longer valid) All DQ and DQS collectively t Notes the lesser DQSQ is derived at each ...

Page 71

Figure 36: x16 Data Output Timing – CK# CK LDQS (last data valid (first data no longer valid (last data valid) ...

Page 72

... WRITE burst (after selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...

Page 73

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of ...

Page 74

Figure 38: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...

Page 75

Figure 39: Consecutive WRITE-to-WRITE T0 CK# CK WRITE Command Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are ...

Page 76

Figure 40: Nonconsecutive WRITE-to-WRITE Command Address t DQSS (NOM) Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following Three ...

Page 77

Figure 42: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...

Page 78

Figure 43: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...

Page 79

Figure 44: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...

Page 80

Figure 45: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...

Page 81

Figure 46: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...

Page 82

Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...

Page 83

Figure 48: Bank WRITE – Without Auto Precharge CKE NOP 1 ACT Command Row Address A10 Row BA0, ...

Page 84

Figure 49: WRITE – DM Operation CKE ACT NOP Command Row Address A10 Row BA0, BA1 Bank ...

Page 85

Figure 50: Data Input Timing CK# CK DQS DQ DM Notes: 1. WRITE command issued at T0 DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during 4. For x16, LDQS controls the lower byte and ...

Page 86

Figure 51: Bank READ – with Auto Precharge CKE ACT NOP Command Address Row A10 Row IS IH BA0, BA1 Bank ...

Page 87

Figure 52: Bank WRITE – with Auto Precharge CKE Command NOP ACT Address Row A10 Row BA0, ...

Page 88

Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends Figure 53: Auto Refresh Mode ...

Page 89

NOPs for 200 additional clock cycles before applying a READ. Any command other than a READ can be performed reset. NOP or DESELECT commands must be issued during the Self refresh is not supported on ...

Page 90

Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend ...

Page 91

Figure 55: Power-Down Mode CK# CK CKE Command Address DQS DQ DM Notes: 1. Once initialized this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is ...

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