MT46V64M8P-6T:F Micron Technology Inc, MT46V64M8P-6T:F Datasheet - Page 52

• Manufacturer Part Number: MT46V64M8P-6T:F
• Description: IC DDR SDRAM 512MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M8P-6T:F

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Organization: 64Mx8
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 175mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operations
INITIALIZATION
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
10. Wait at least
11. Using the LMR command, program the mode register to set operating parameters
12. Wait at least
13. Issue a PRECHARGE ALL command.
14. Wait at least
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least
19. Although not required by the Micron device, JEDEC requires an LMR command to
20. Wait at least
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
1. Simultaneously apply power to V
2. Apply V
3. Assert and hold CKE at a LVCMOS logic LOW. Maintaining an LVCMOS LOW level on
4. Provide stable clock signals.
5. Wait at least 200µs.
6. Bring CKE HIGH, and provide at least one NOP or DESELECT command. At this
7. Perform a PRECHARGE ALL command.
8. Wait at least
9. Using the LMR command, program the extended mode register (E0 = 0 to enable the
Prior to normal operation, DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures, other than those specified, may result in
undefined operation.
To ensure device operation, the DRAM must be initialized as described in the following
steps:
up, which may cause permanent damage to the device. Except for CKE, inputs are not
recognized as valid until after V
CKE during power-up is required to ensure that the DQ and DQS outputs will be in
the High-Z state, where they will remain until driven in normal operation (by a read
access).
point, the CKE input changes from a LVCMOS input to a SSTL_2 input only and will
remain a SSTL_2 input unless a power cycle occurs.
DLL and E1 = 0 for normal drive; or E1 = 1 for reduced drive and E2–En must be set to
0 [where n = most significant bit]).
and to reset the DLL. At least 200 clock cycles are required between a DLL reset and
any READ command.
clear the DLL bit (set M8 = 0). If an LMR command is issued, the same operating
parameters should be utilized as in step 11.
CKE HIGH are required between step 11 (DLL RESET) and any READ command.
REF
and then V
t
t
t
t
t
t
t
RP time; during this time NOPs or DESELECT commands must be given.
MRD time; only NOPs or DESELECT commands are allowed.
MRD time; only NOPs or DESELECT commands are allowed.
RP time; only NOPs or DESELECT commands are allowed.
RFC time; only NOPs or DESELECT commands are allowed.
RFC time; only NOPs or DESELECT commands are allowed.
MRD time; only NOPs or DESELECT commands are supported.
TT
power. V
52
REF
DD
TT
is applied.
must be applied after V
and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
512Mb: x4, x8, x16 DDR SDRAM
Q.
DD
©2000 Micron Technology, Inc. All rights reserved.
Q to avoid device latch-
Operations