MT48LC4M16A2P-7E:G Micron Technology Inc, MT48LC4M16A2P-7E:G Datasheet - Page 20

• Manufacturer Part Number: MT48LC4M16A2P-7E:G
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC4M16A2P-7E:G

• Density: 64 Mb
• Maximum Clock Rate: 143 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 4Mx16
• Address Bus: 14b
• Access Time (max): 5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-
sistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in “Operation” on
page 21.
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the Operation section of this data
sheet. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
PRECHARGE command as shown in the Operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the
64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and indus-
trial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every
15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the refresh
requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate (
(commercial and industrial) or 16ms (automotive).
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
for an indefinite period beyond that.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RAS and may remain in self refresh mode
t
RP has been met after the
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
t
RFC), once every 64ms
Commands