MT48LC4M16A2TG-75 IT:G TR Micron Technology Inc, MT48LC4M16A2TG-75 IT:G TR Datasheet - Page 26

• Manufacturer Part Number: MT48LC4M16A2TG-75 IT:G TR
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M16A2TG-75 IT:G TR

• Package: 54TSOP-II
• Density: 64 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1090-2

Figure 13:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Random READ Accesses
Note:
COMMAND
COMMAND
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figures 14 and 15 on
page 27. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in,
then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
BANK,
T0
COL n
BANK,
COL n
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
BANK,
BANK,
READ
COL a
READ
COL a
26
T2
BANK,
T2
COL x
BANK,
READ
READ
COL x
D
OUT
n
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
BANK,
COL m
READ
READ
BANK,
COL m
D
D
OUT
a
OUT
n
T4
T4
NOP
NOP
D
D
OUT
x
OUT
a
64Mb: x4, x8, x16 SDRAM
T5
T5
NOP
NOP
D
D
m
OUT
OUT
x
©2000 Micron Technology, Inc. All rights reserved.
DON’T CARE
T6
NOP
D
OUT
m
Commands