MT48LC4M16A2TG-75 IT:G TR Micron Technology Inc, MT48LC4M16A2TG-75 IT:G TR Datasheet - Page 32

DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R

MT48LC4M16A2TG-75 IT:G TR

Manufacturer Part Number
MT48LC4M16A2TG-75 IT:G TR
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M16A2TG-75 IT:G TR

Package
54TSOP-II
Density
64 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1090-2
Figure 21:
Figure 22:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Random WRITE Cycles
WRITE-to-READ
Note:
Note:
COMMAND
COMMAND
ADDRESS
ADDRESS
Each WRITE command may be to any bank. DQM is LOW.
The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW. CL = 2 for illustration.
CLK
CLK
DQ
DQ
TRANSITIONING DATA
WRITE
BANK,
BANK,
COL n
WRITE
COL n
D
T0
D
T0
n
n
IN
IN
WRITE
BANK,
n + 1
COL a
NOP
D
T1
T1
D
a
IN
IN
TRANSITIONING DATA
WRITE
BANK,
COL x
BANK,
COL b
READ
T2
T2
D
x
IN
32
DON’T CARE
WRITE
COL m
BANK,
T3
T3
NOP
D
m
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
D
T4
OUT
b
DON’T CARE
NOP
T5
b + 1
D
OUT
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands

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