MT48LC4M16A2TG-75 IT:G TR Micron Technology Inc, MT48LC4M16A2TG-75 IT:G TR Datasheet - Page 57

• Manufacturer Part Number: MT48LC4M16A2TG-75 IT:G TR
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M16A2TG-75 IT:G TR

• Package: 54TSOP-II
• Density: 64 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1090-2

Figure 40:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
READ – Without Auto Precharge
ACTIVE
ROW
ROW
BANK
T0
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual”
2. x16: A8, A9 and A11 = “Don’t Care”
DISABLE AUTO PRECHARGE
PRECHARGE.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CMS
t CL
COLUMN m
BANK
T2
READ
t CMH
t CH
CAS Latency
2
T3
NOP
t LZ
t AC
57
T4
D
NOP
OUT
t OH
t AC
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
t OH
m+1
t AC
SINGLE BANKS
ALL BANKS
PRECHARGE
BANK(S)
D
T6
OUT
t OH
64Mb: x4, x8, x16 SDRAM
m+2
t RP
t AC
©2000 Micron Technology, Inc. All rights reserved.
D
T7
NOP
OUT
t OH
m+3
Timing Diagrams
t HZ
BANK
ACTIVE
ROW
ROW
T8
DON’T CARE
UNDEFINED