M29DW128G70NF6E NUMONYX, M29DW128G70NF6E Datasheet - Page 14

no-image

M29DW128G70NF6E

Manufacturer Part Number
M29DW128G70NF6E
Description
P7ED TSOP56 DUAL BANK
Manufacturer
NUMONYX
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M29DW128G70NF6E
Manufacturer:
MICRON
Quantity:
1 000
Part Number:
M29DW128G70NF6E
Manufacturer:
ST
0
Part Number:
M29DW128G70NF6E
Manufacturer:
MICRON/美光
Quantity:
20 000
Signal descriptions
2.7
2.8
14/85
When V
the four outermost blocks. Program and erase operations can now modify the data in these
blocks unless the blocks are protected using block protection.
When V
bypass mode (see
When V
Table 12: Program, erase times and program, erase endurance
When V
bypass program operations the memory draws I
circuits. See the description of the Unlock Bypass command in the command interface
section. The transitions from V
(see
Never raise V
memory may be left in an indeterminate state. A 0.1 µF capacitor should be connected
between the V
from the power supply. The PCB track widths must be sufficient to carry the currents
required during unlock bypass program (see I
characteristics).
The V
pull-up.
Refer to
Table 3.
1. Two at the top and two at the bottom of the address space.
Reset (RP)
The reset pin can be used to apply a hardware reset to the memory.
A hardware reset is achieved by holding reset Low, V
High, V
t
characteristics,
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, V
mode, auto select mode and erase suspend mode.
RHEL
Figure 19: Accelerated program timing
, whichever occurs last. See
PP
V
OL
IH
PP
PP
V
PP
PP
PP
/write protect pin may be left floating or unconnected because it features an internal
Table 3
V
V
, the memory will be ready for bus read and bus write operations after t
PPH
(see
/WP
IH
IL
/write protect is High, V
/write protect is raised to V
/write protect is raised to V
/write protect returns to V
V
PP
PP
Table 15: Status register
PP
Figure 17
/write protect to V
for a summary of V
/write protect pin and the V
/WP functions
Section
Four outermost blocks
Four outermost blocks
activated (see
Unlock bypass mode. It supplies the current needed to speed up
programming.
and
7.2.6).
Figure 18
IH
to V
PPH
IH
Section 2.8: Ready/busy output
Section 5: Hardware
, the memory reverts to the previous protection status of
PP
IH
PPH
PPH
PPH
from any mode except read mode, otherwise the
/WP functions.
or V
bits). Ready/busy is high-impedance during read
for more details.
, the execution time of the command is lower (see
and from V
(1)
(1)
the memory automatically enters the unlock
IL
SS
protected.
unprotected unless a software protection is
waveforms).
normal operation resumes. During unlock
PP1
ground pin to decouple the current surges
PP
, I
PP2
from the pin to supply the programming
Function
PPH
IL
protection).
, I
, for at least t
PP3
to V
, I
IH
PP4
must be slower than t
cycles).
in
(RB),
PLPX
Table 22: DC
Table 26: Reset AC
. After reset goes
M29DW128G
PHEL
VHVPP
or

Related parts for M29DW128G70NF6E