C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 231

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
SCK
SCR7
f
SCK
R/W
Bit7
R/W
Bit7
=
=
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
f
200kHz
SCK
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
------------------------- -
2
2000000
SCR6

R/W
Bit6

=
R/W
Bit6
4
+
------------------------------------------------ -
2

1
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate


SPI0CKR
SCR5
SYSCLK
R/W
Bit5
SFR Definition 20.4. SPI0DAT: SPI0 Data
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SCR4
+
R/W
Bit4
1
R/W
Bit4

SCR3
Rev. 1.3
R/W
Bit3
R/W
Bit3
SCR2
R/W
Bit2
R/W
Bit2
SCR1
R/W
Bit1
R/W
Bit1
SFR Address: 0xA2
SFR Address: 0xA3
SCR0
R/W
Bit0
R/W
Bit0
00000000
Reset Value
00000000
Reset Value
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