C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 266
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C8051F340-GQR
Manufacturer Part Number
C8051F340-GQR
Description
MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F340-GQR.pdf
(276 pages)
Specifications of C8051F340-GQR
Package
48TQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
40
Interface Type
I2C/SMBus/SPI/UART/USB
On-chip Adc
17-chx10-bit
Number Of Timers
4
Ram Size
4.25 KB
Program Memory Size
64 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
22.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
266
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
CF
Bit7
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
UNUSED. Read = 0b, Write = don't care.
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
CR
Bit6
SFR Definition 22.1. PCA0CN: PCA Control
R/W
Bit5
-
CCF4
R/W
Bit4
Rev. 1.3
CCF3
R/W
Bit3
CCF2
R/W
Bit2
CCF1
R/W
Bit1
(bit addressable)
CCF0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xD8
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