P87C52X2BA NXP Semiconductors, P87C52X2BA Datasheet - Page 36

• Manufacturer Part Number: P87C52X2BA
• Description: MCU 8-Bit 87C 80C51 CISC 8KB EPROM 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C52X2BA

• Package: 44PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Program Memory Type: EPROM
• Operating Temperature: 0 to 70 °C

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
Table 8.
NOTES:
Reduced EMI
All port pins have slew rate controlled outputs. This is to limit noise
generated by quickly switching output signals. The slew rate is
factory set to approximately 10 ns rise and fall times.
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
AUXR (8EH)
AUXR.0
Dual DPTR
The dual DPTR structure (see Figure 26) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
AUXR1 (A2H)
Where:
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
2003 Jan 24
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxx000x0B
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
7
–
7
–
External interrupt 0
External interrupt 1
SOURCE
Timer 0
Timer 1
Timer 2
UART
6
–
Select Reg
6
–
DPTR0
DPTR1
AO
Interrupt Table
5
–
5
–
4
–
LPEP
4
Turns off ALE output.
POLLING PRIORITY
WUPD
3
–
3
1
2
3
4
5
6
2
–
2
0
DPS
0
1
1
–
1
–
AO
DPS
REQUEST BITS
0
0
TF2, EXF2
RI, TI
TF0
TF1
IE0
IE1
36
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WUPD or LPEP bits.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
INC DPTR
MOV DPTR, #data16
MOV A, @ A+DPTR
MOVX A, @ DPTR
MOVX @ DPTR , A
JMP @ A + DPTR
AUXR1
DPS
BIT0
HARDWARE CLEAR?
N (L)
N (L) Y (T)
1
(83H)
DPH
Y
Y
N
N
Increments the data pointer by 1
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
Move ACC to external RAM (16-bit
address)
Jump indirect relative to DPTR
Y (T)
P80C3xX2; P80C5xX2;
Figure 26.
(82H)
2
DPL
DPTR1
DPTR0
VECTOR ADDRESS
P87C5xX2
0BH
1BH
2BH
EXTERNAL
03H
13H
23H
MEMORY
DATA
Product data
SU00745A