XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 12

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Spartan-IIE FPGA Family: Functional Description
is required for most output standards and for LVTTL,
LVCMOS, and PCI inputs.
Table 4: Compatible Standards
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
one in six of the I/O pins in the bank assume this role.
V
consequently only one V
each bank. All V
nected to the external voltage source for correct operation.
In a bank, inputs requiring V
that do not but only one V
bank. The V
device pinout tables.
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
a superset of the V
possible to design a PCB that permits migration to a larger
device. All V
be connected to the V
Table 5: I/O Banking
See Xilinx
on I/O resources.
12
V
V
REF
V
CCO
REF
3.3V
2.5V
1.8V
1.5V
Package
CCO
pins within a bank are interconnected internally and
Banks
Banks
®
REF
Application Note
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
LVPECL, GTL, GTL+
SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus
LVDS, GTL, GTL+
LVCMOS18, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
CCO
REF
. In this case, certain user-I/O pins are auto-
REF
pins for the largest device anticipated must
and V
Interconnected as 1
REF
TQ144, PQ208
pins in the bank, however, must be con-
8 independent
REF
REF
Compatible Standards
pins used for smaller devices, it is
REF
REF
REF
voltage, and not used for I/O.
pins for each bank appear in the
XAPP179
REF
voltage may be used within a
pins. Since these are always
voltage can be used within
can be mixed with those
for more information
REF
REF
FT256, FG456,
8 independent
8 independent
and V
voltage. About
FG676
CCO
www.xilinx.com
pins
Hot Swap, Hot Insertion, Hot Socketing Support
The I/O pins support hot swap — also called hot insertion
and hot socketing — and are considered CompactPCI
Friendly according to the PCI Bus v2.2 Specification. Con-
sequently, an unpowered Spartan-IIE FPGA can be
plugged directly into a powered system or backplane with-
out affecting or damaging the system or the FPGA. The hot
swap
XC2S400E, and XC2S600E device. All other Spartan-IIE
devices built after Product Change Notice
include hot swap functionality.
To support hot swap, Spartan-IIE devices include the follow-
ing I/O features.
•
•
•
•
Once connected to the system, each pin adds a small
amount of capacitance (C
a small amount of DC current, equivalent to the input leak-
age specification (I
temporary AC current (I
exceeds V
A weak-keeper circuit within each user-I/O pin is enabled
during the last frame of configuration data and has no
noticeable effect on robust system signals driven by an
active driver or a strong pull-up or pull-down resistor.
Undriven or floating system signals may be affected. The
specific effect depends on how the I/O pin is configured.
User-I/O pins configured as outputs or enabled outputs
have a weak pull-up resistor to V
uration frame. User-I/O pins configured as inputs or bidirec-
tional I/Os have weak pull-down resistors. The weak-keeper
circuit turns off when the DONE pin goes High, provided
that it is not used in the configured application.
Signals can be applied to Spartan-IIE FPGA I/O pins
before powering the FPGA’s V
inputs.
Spartan-IIE FPGA I/O pins are high-impedance (i.e.,
three-stated) before and throughout the power-up and
configuration processes when employing a
configuration mode that does not enable the
preconfiguration weak pull-up resistors (see
page
There is no current path from the I/O pin back to the
V
Spartan-IIE FPGAs are immune to latch-up during hot
swap.
CCINT
functionality
22).
CCO
or V
plus 0.4V, which lasts less than 10 ns.
CCO
L
). There also may be a small amount of
voltage supplies.
is
HSPO
IN
built
). Likewise, each I/O consumes
) when the pin input voltage
DS077-2 (v2.3) June 18, 2008
CCO
into
CCINT
during the last config-
Product Specification
every
or V
PCN2002-05
CCO
XC2S150E,
Table 11,
supply
also
R