XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 88

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
FG456 Differential Clock Pins
Additional FG456 Package Pins
88
Notes:
1.
I/O,
L#P_YY
I/O, VREF
Bank 0,
L#N_YY
I/O
I/O, L#P
I/O, L#N
I/O
I/O, L#P
I/O, L#N
I/O
I/O, L#P
I/O, L#N
I/O
I/O
TCK
VCCINT Pins
VCCO Bank 0 Pins
Function Bank
Pad Name
Although designated with the _YY suffix in the XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these differential pairs are not
asynchronous in the XC2S400E.
D4
G16
U6
F7
GCK0
GCK1
GCK2
GCK3
Clock
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Pin
A6
B6
C6
A5
B5
D6
B4
C5
A4
A3
B3
C4
D5
E6
D19
U17
H7
F8
(1)
200E, 300E,
200E, 300E,
XC2S100E,
400E, 600E
XC2S100E,
400E, 600E
XC2S150E,
400E, 600E
XC2S150E,
400E, 600E
XC2S100E
XC2S100E
Bank
Async.
Output
Option
LVDS
4
5
1
0
All
All
-
-
-
-
-
-
H16
G9
E5
V5
XC2S200E,
400E, 600E
Option
300E,
V
All
REF
AA12
AB12
-
-
-
-
-
-
-
-
-
-
-
-
C11
A11
Pin
E18
V18
G10
R7
I/O, L1P_Y
I/O, L1N_Y
I/O, L0P_Y
I/O, L0N_Y
I/O, VREF
L2P_YY
L2N_YY
Bank 0,
100E
TCK
I/O,
www.xilinx.com
I/O
I/O
-
-
-
-
-
P
W4
R16
GCK0, I
GCK1, I
GCK2, I
GCK3, I
F6
Name
-
I/O, L0P_Y
I/O, L0N_Y
(1)
I/O, VREF
L3P_YY
L3N_YY
I/O, L2P
I/O, L2N
I/O, L1P
I/O, L1N
Bank 0,
150E
TCK
I/O,
I/O
I/O
I/O
-
-
Device-Specific Pinouts: XC2S
W19
F17
T7
I/O, L1P_Y
-
I/O, VREF
I/O, VREF
L3N_YY
I/O, L2N
I/O, L0N
L3P_YY
I/O, L2P
I/O, L0P
Bank 0,
Bank 0,
(1)
L1N_Y
200E
TCK
I/O,
I/O
I/O
I/O
-
-
AB11
Y12
A12
B11
Pin
I/O, L1P_Y
G7
T8
I/O, VREF
I/O, VREF
-
-
L3P_YY
L3N_YY
I/O, L2P
I/O, L2N
I/O, L0P
I/O, L0N
Bank 0,
Bank 0,
L1N_Y
300E
TCK
I/O,
I/O
I/O
I/O
I/O
I/O
DS077-4 (2.3) June 18, 2008
N
I/O, L0N_Y
I/O, L1P_Y
I/O, L0P_Y
I/O, VREF
I/O, VREF
I/O (DLL), L#N
I/O (DLL), L#N
T15
I/O (DLL), L#P
I/O (DLL), L#P
G8
L3N_YY
I/O, L2N
L3P_YY
I/O, L2P
Bank 0,
Bank 0,
Product Specification
L1N_Y
-
-
400E
TCK
I/O,
I/O
I/O
I/O
I/O
I/O
Name
I/O, L1P_Y
I/O, L0P_Y
I/O, L0N_Y
I/O, VREF
I/O, VREF
L3N_YY
L3P_YY
I/O, L2P
I/O, L2N
G15
Bank 0,
Bank 0,
T16
L1N_Y
600E
TCK
-
-
I/O,
I/O
I/O
I/O
I/O
I/O
R