XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 42

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Spartan-IIE FPGA Family: DC and Switching Characteristics
Clock Distribution Switching Characteristics
T
Input
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
42
Notes:
1.
GCLK IOB and Buffer
Data Input Delay Adjustments
GPIO
T
T
Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table
T
T
GPLVCMOS18
T
T
GPLVCMOS2
T
T
T
Adjustments.
T
T
Symbol
GPPCI33_3
GPPCI66_3
GPLVPECL
Symbol
T
T
T
is specified for LVTTL levels. For other standards, adjust T
GPLVCDS
GPSSTL2
GPSSTL3
GPLVTTL
T
GPGTLP
GPHSTL
GPGTL
GPCTT
GPAGP
T
GPIO
GIO
Global clock pad to output
Global clock buffer I input to O output
Standard-specific global clock
input delay adjustments
Description
Description
www.xilinx.com
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
LVCMOS18
LVCMOS2
LVCPECL
Standard
GPIO
SSTL2
SSTL3
LVTTL
LVDS
GTL+
HSTL
AGP
GTL
CTT
with the values shown in
Delay Measurement Methodology, page
–0.11
Max
0.45
0.38
0.38
0.08
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.7
0.2
-7
-7
0
0
Speed Grade
Speed Grade
DS077-3 (v2.3) June 18, 2008
I/O Standard Global Clock
–0.11
Max
0.38
0.38
0.08
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.7
0.5
0.2
Product Specification
-6
-6
0
0
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41.
R