XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 24

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Spartan-IIE FPGA Family: Functional Description
During start-up, the device performs four operations:
1. The assertion of DONE. The failure of DONE to go High
2. The release of the Global Three State (GTS). This
3. The release of the Global Set Reset (GSR). This allows
4. The assertion of Global Write Enable (GWE). This
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
four operations can be selected to switch on any CCLK
cycle
Development Software. The default timing for start-up is
shown in the top half of
settings.
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
The bottom half of
used
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
The sequence can also be paused at any stage until lock
has been achieved on any or all DLLs.
24
may indicate the unsuccessful loading of configuration
data.
activates all the I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-up resistors present.
all flip-flops to change state.
allows all RAMs and flip-flops to change state.
version
C1-C6
of
through
Figure 17
the
Figure
start-up
settings
17; heavy lines show default
shows another commonly
timing
in
the
known
Xilinx
www.xilinx.com
as
Serial Modes
There are two serial configuration modes. In Master Serial
mode, the FPGA controls the configuration process by driv-
ing CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per CCLK
cycle. The MSB of each configuration data byte is always
written to the DIN pin first.
See
Spartan-IIE FPGA serially. This is an expansion of the
"Load Configuration Data Frames" block in
page
during serial configuration. To ensure successful loading of
the FPGA, do not toggle WRITE with CS Low during serial
configuration.
Figure 18
23. Note that CS and WRITE are not normally used
Start-up CLK
Start-up CLK
Phase
DONE
Phase
DONE
Figure 17: Start-Up Waveforms
GWE
GWE
GSR
GSR
GTS
GTS
for the sequence for loading data into the
DONE High
0
0
1
1
Default Cycles
Sync to DONE
2
2
DS077-2 (v2.3) June 18, 2008
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3
4
4
Product Specification
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5
DS001_13_090600
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Figure 16,
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