LFE3-35EA-6FN484I LATTICE SEMICONDUCTOR, LFE3-35EA-6FN484I Datasheet - Page 28

• Manufacturer Part Number: LFE3-35EA-6FN484I
• Description: FPGA LatticeECP3™ Family 33000 Cells 65nm Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE3-35EA-6FN484I

• Package: 484FBGA
• Family Name: LatticeECP3™
• Device Logic Units: 33000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 295
• Ram Bits: 1358848

Lattice Semiconductor
MAC DSP Element
In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated
value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but
the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-
figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-
tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27
shows the MAC sysDSP element.
Figure 2-27. MAC DSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
I
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-25
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
PR
OR
IR
BB
IR
COUT
SROB
SROA
DSP Slice
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Architecture