SC26C92C1A NXP Semiconductors, SC26C92C1A Datasheet
SC26C92C1A
Specifications of SC26C92C1A
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SC26C92C1A Summary of contents
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... SC26C92 Dual universal asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1998 Nov 09 IC19 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 2000 Jan 31 ...
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... Detects break which originates in the middle of a character On-chip crystal oscillator Power down mode Receiver timeout mode Single +5V power supply Powers up to emulate SCC2692 1 COMMERCIAL V = + +5V 10 SC26C92C1N SC26C92C1A SC26C92C1B 2 Product specification SC26C92 INDUSTRIAL DWG # DWG # = - SC26C92A1N SOT129-1 SC26C92A1A SOT187-2 SC26C92A1B SOT307–2 853–1585 23061 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) NOTE: 1. Commercial devices are tested for the –40 to +85 C. PIN CONFIGURATIONS IP3 2 39 IP4 IP5 IP1 4 37 IP6 IP2 CEN IP0 7 34 RESET WRN RDN 9 32 X1/CLK RxDB 10 31 RxDA DIP TxDB 11 30 TxDA ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM 8 D0–D7 BUS BUFFER OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 4 A0–A3 R/W CONTROL RESET INTERRUPT CONTROL INTRN IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER X1/CLK XTAL OSC ...
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... CPU the least significant bit. CEN X I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines in the 3-State condition. WRN ...
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... Typical values are at +25 C, typical supply voltages, and typical processing parameters. 3. Test conditions for outputs 150pF, except interrupt outputs. Test conditions for interrupt outputs All outputs are disconnected. Inputs are switching between CMOS levels See UART application note for power down currents less. 2000 Jan 31 PARAMETER 2 3 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART CHARACTERISTICS 10 – unless otherwise specified SYMBOL Reset Timing (See Figure 3) t RESET pulse width RES 5 Bus Timing (See Figure 4) t A0-A3 setup time to RDN, WRN Low AS t A0-A3 hold time from RDN, WRN Low ...
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... The Counter/Timer is a programmable 16–bit divider that is used for generating miscellaneous clocks or generating timeout periods. These clocks may be used by any or all of the receivers and trans- mitters in the DUART or may be directed to an I/O pin for miscella- neous use. Counter/Timer programming The counter timer is a 16–bit programmable divider that operates in one of three modes: counter, timer, and time out ...
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... Low input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic or modem and DMA control. Four change-of-state detectors are provided which are associated with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High transition of these inputs, lasting longer than will set the corresponding bit in the input port change register ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) This feature may be used automatically “turnaround” a transceiver when operating in a simplex system. Transmitter Disable Note (W.R.T. Turnaround) When the TxEMT bit is set the sequence of instructions: enable transmitter — load transmit holding register — disable transmitter will often result in nothing being sent ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) seen. At this point the host has approximately 6/16–bit time to read a byte from the RxFIFO or the overrun condition will be set. The character then overruns the 9 and the 11 until an open position in the RxFIFO is seen. (“seen” meaning at least one byte was read from the RxFIFO.) Overrun is cleared by a use of the “ ...
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... SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled. PROGRAMMING The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 2 for register bit descriptions. Table 1. SC26C92 Register Addressing NOTE: The three MR Registers are accessed via the MR Pointer and Commands 1xh and Bxh. (Where “x” represents receiver and transmitter enable/ ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) BIT 7 BIT 6 CHANNEL MODE MR2A MR2B MR2B 00 = Normal 0x00 01 = Auto-Echo 10 = Local loop 11 = Remote loop NOTE: *Add 0.5 to values shown for 0 – channel is programmed for 5 bits/char. BIT 7 BIT 6 CSRA CSRA CSRB RECEIVER CLOCK SELECT 0x01 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats (Continued) BIT 7 BIT 6 SRA RECEIVED FRAMING SRB BREAK* ERROR* 0x01 Yes 1 = Yes NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “ ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) BIT 7 BIT 6 CTPU CTPU C/T[15] C/T[14] 0x06 0x06 BIT 7 BIT 6 CTPL CTPL C/T[7] C/T[6] 0x07 0x07 REGISTER DESCRIPTIONS Mode Registers MR0 is accessed by setting the MR pointer to 0 via the command register command B. MR0A MR0[7] – This bit controls the receiver watch dog timer disable enable ...
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... MR1A. Accesses to MR2A do not change the pointer. MR2A[7:6] – Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7: the normal mode, with the transmitter and receiver operating independently. MR2A[7: places the channel in the automatic echo mode, which automatically retransmits the received data ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) applied via CRB. After reading or writing MR0B, the pointer will point to MR1B. The bit definitions for this register are identical to MR0A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. MR0B[3:0] are reserved. ...
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... Counter’ command should be issued to force a reset of the ISR(3) bit. 1101 Not used. 1110 Power Down Mode On. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires a X1/CLK ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) SRA[6] – Channel A Framing Error This bit, when set, indicates that a stop bit was not detected (not a logical 1) when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. SRA[5] – ...
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... ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset. 21 Product specification ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR. ISR[6] – ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) RESETN A0– CEN t CS RDN D0–D7 FLOAT (READ) WDN D0–D7 (WRITE) RDN IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 2000 Jan 31 t RES SD00133 Figure 3. Reset Timing RWD NOT VALID FLOAT VALID ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) WRN INTERRUPT OUTPUT RDN INTERRUPT OUTPUT NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal point 0 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) TxC (INPUT) TxD TxC (1X OUTPUT) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) WRN CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 2000 Jan 31 1 BIT TIME ( CLOCKS) ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP5) RDN STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR( and MR( MASTER STATION ADD#1 TxD TRANSMITTER ENABLED TxRDY ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) 2.7K INTRN 50pF + 2.4mA 400 A V D0–D7 TxDA/B OP0–OP7 150pF Figure 13. Test Conditions on Outputs 2000 Jan 31 + SD00157 27 Product specification SC26C92 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 2000 Jan 31 28 Product specification SC26C92 SOT129-1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2000 Jan 31 29 Product specification SC26C92 SOT187-2 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 2000 Jan 31 30 Product specification SC26C92 SOT307-2 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. ...